uart_regs.vm

vlsi UART referene, use UART0_3

assign mcr8 = (~addr_i_c[1] & mcr8_2 & we_i_c);
assign un1_rda_int_1_0 = (N_208_1 & ~iir67_sn & ~ms_int_pnd & ~thre_int_pnd);
assign N_259 = (~block_cnt[0] & ~block_cnt[1] & un1_thre_set_en_0 & un1_thre_set_en_4);
assign un1_dl_12 = (~dl[6] & ~dl[7] & un1_dl_0 & un1_dl_10);
assign un1_dlc_12 = (un1_dlc_10 & un1_dlc_11);
assign block_cnt_5[5] = (lcr[0] & ~lcr[1] & ~lcr[2]) | (~lcr[0] & ~lcr[1] & 
   lcr[2]) | (lcr[0] & ~lcr[1] & ~lcr[3]) | (lcr[0] & ~lcr[1] & ~lcr[2] & 
   ~lcr[3]) | (~lcr[0] & lcr[1] & ~lcr[2] & ~lcr[3]) | (~lcr[1] & lcr[2] & 
   ~lcr[3]) | (~lcr[0] & ~lcr[1] & lcr[3]) | (~lcr[1] & ~lcr[2] & lcr[3]) | 
   (~lcr[0] & ~lcr[1] & lcr[2] & lcr[3]) | (lcr[0] & lcr[1] & lcr[2] & 
   lcr[3]);
assign block_cnt_5[6] = (~lcr[0] & ~lcr[1]) | (~lcr[1] & ~lcr[2]) | (~lcr[0] & 
   ~lcr[1] & lcr[2]) | (~lcr[1] & ~lcr[3]) | (~lcr[0] & ~lcr[2] & ~lcr[3]) | 
   (~lcr[1] & ~lcr[2] & ~lcr[3]) | (~lcr[0] & lcr[1] & ~lcr[2] & ~lcr[3]) | 
   (~lcr[1] & lcr[2] & ~lcr[3]) | (~lcr[0] & ~lcr[1] & lcr[3]) | (~lcr[1] & 
   ~lcr[2] & lcr[3]) | (~lcr[0] & ~lcr[1] & lcr[2] & lcr[3]);
assign N_192_i = (rls_int_pnd) | (rls_int_pnd & ~thre_int_pnd) | (~iir67_sn & 
   ~rda_int & thre_int_pnd) | (~iir67_sn & ~rda_int & ~rls_int_pnd & thre_int_pnd) | 
   (rls_int_pnd & thre_int_pnd);
assign N_208_i = (iir67_sn) | (iir67_sn & ~rls_int_pnd) | (rls_int_pnd) | 
   (ier[0] & ~un5_rda_int_cry_4) | (ier[0] & ~iir67_sn & ~un5_rda_int_cry_4) | 
   (iir67_sn & ~un5_rda_int_cry_4) | (ier[0] & ~rls_int_pnd & ~un5_rda_int_cry_4) | 
   (ier[0] & ~iir67_sn & ~rls_int_pnd & ~un5_rda_int_cry_4) | (iir67_sn & 
   ~rls_int_pnd & ~un5_rda_int_cry_4) | (rls_int_pnd & ~un5_rda_int_cry_4) | 
   (iir67_sn & un5_rda_int_cry_4) | (iir67_sn & ~rls_int_pnd & un5_rda_int_cry_4) | 
   (rls_int_pnd & un5_rda_int_cry_4);
assign un13_rda_int_pnd_i_m_i = (ier[0] & rda_int_pnd) | (ier[0] & ~rda_int_d & 
   ~un5_rda_int_cry_4) | (ier[0] & ~rda_int_d & ~rda_int_pnd & ~un5_rda_int_cry_4) | 
   (ier[0] & rda_int_pnd & ~un5_rda_int_cry_4) | (ier[0] & rda_int_pnd & 
   un5_rda_int_cry_4);
assign tx_reset11 = (dat_o31 & we_i_c);
assign fifo_read = (~addr_i_c[0] & dl15_1 & ~lcr[7] & re_i_c);
assign ier_1_sqmuxa = (addr_i_c[0] & dl15_1 & ~lcr[7] & we_i_c);
assign ier_0_sqmuxa = (addr_i_c[0] & dl15_1 & lcr[7] & we_i_c);
assign msi_reset13 = (~msi_reset & msr_read);
assign ms_int_rise = (ms_int & ~ms_int_d);
assign N_214 = (un1_dlc_8 & un1_dlc_9 & un1_dlc_10 & un1_dlc_11);
assign enable10 = (N_214 & ~un1_dl_8) | (N_214 & ~un1_dl_9) | (N_214 & 
   ~un1_dl_8 & un1_dl_9) | (N_214 & ~un1_dl_12) | (N_214 & ~un1_dl_8 & 
   un1_dl_12) | (N_214 & ~un1_dl_9 & un1_dl_12) | (N_214 & ~un1_dl_8 & 
   un1_dl_9 & un1_dl_12);
assign dl_0_sqmuxa = (~addr_i_c[0] & dl15_1 & lcr[7] & we_i_c);
assign fifo_write = (~addr_i_c[0] & dl15_1 & ~lcr[7] & we_i_c);
assign N_211 = (~start_dlc & ~un1_dlc_8) | (~start_dlc & ~un1_dlc_9) | 
   (~start_dlc & ~un1_dlc_8 & un1_dlc_9) | (~start_dlc & ~un1_dlc_12) | 
   (~start_dlc & ~un1_dlc_8 & un1_dlc_12) | (~start_dlc & ~un1_dlc_9 & 
   un1_dlc_12) | (~start_dlc & ~un1_dlc_8 & un1_dlc_9 & un1_dlc_12);
assign block_cnt_lm[0] = (block_cnt_s[0]) | (block_cnt_s[0] & ~dl15_1) | 
   (~addr_i_c[0] & block_cnt14_1 & dl15_1) | (~addr_i_c[0] & block_cnt14_1 & 
   ~block_cnt_s[0] & dl15_1) | (block_cnt_s[0] & dl15_1);
assign block_cnt_lm[1] = (block_cnt_s[1]) | (block_cnt_s[1] & ~dl15_1) | 
   (~addr_i_c[0] & block_cnt14_1 & dl15_1) | (~addr_i_c[0] & block_cnt14_1 & 
   ~block_cnt_s[1] & dl15_1) | (block_cnt_s[1] & dl15_1);
assign block_cnt_lm[2] = (block_cnt_s[2]) | (block_cnt_s[2] & ~dl15_1) | 
   (~addr_i_c[0] & block_cnt14_1 & dl15_1) | (~addr_i_c[0] & block_cnt14_1 & 
   ~block_cnt_s[2] & dl15_1) | (block_cnt_s[2] & dl15_1);
assign un13_ti_int_pnd_iv[0] = (~fifo_read & ier[0] & iir67_sn);
assign un13_rls_int_pnd_iv[0] = (ier[2] & ~lsr_mask_condition & rls_int_pnd) | 
   (ier[2] & ~lsr_mask_condition & ~lsr_mask_d & rls_int_pnd) | (ier[2] & 
   lsr_mask_d & rls_int_pnd);
assign block_cnt_lm[3] = (~block_cnt14_1 & block_cnt_s[3]) | (~m2 & block_cnt_s[3]) | 
   (~block_cnt14_1 & m2 & block_cnt_s[3]) | (block_cnt_s[3] & ~dat_o29) | 
   (block_cnt14_1 & ~m2 & dat_o29) | (block_cnt14_1 & ~m2 & ~block_cnt_s[3] & 
   dat_o29) | (~block_cnt14_1 & block_cnt_s[3] & dat_o29) | (~m2 & block_cnt_s[3] & 
   dat_o29) | (~block_cnt14_1 & m2 & block_cnt_s[3] & dat_o29);
assign block_cnt_lm[4] = (~block_cnt14_1 & block_cnt_s[4]) | (~block_cnt14_1 & 
   ~block_cnt_5[4] & block_cnt_s[4]) | (block_cnt_5[4] & block_cnt_s[4]) | 
   (block_cnt_s[4] & ~dat_o29) | (block_cnt14_1 & block_cnt_5[4] & dat_o29) | 
   (block_cnt14_1 & block_cnt_5[4] & ~block_cnt_s[4] & dat_o29) | (~block_cnt14_1 & 
   block_cnt_s[4] & dat_o29) | (~block_cnt14_1 & ~block_cnt_5[4] & block_cnt_s[4] & 
   dat_o29) | (block_cnt_5[4] & block_cnt_s[4] & dat_o29);
assign block_cnt_lm[5] = (~block_cnt14_1 & block_cnt_s[5]) | (~block_cnt14_1 & 
   ~block_cnt_5[5] & block_cnt_s[5]) | (block_cnt_5[5] & block_cnt_s[5]) | 
   (block_cnt_s[5] & ~dat_o29) | (block_cnt14_1 & block_cnt_5[5] & dat_o29) | 
   (block_cnt14_1 & block_cnt_5[5] & ~block_cnt_s[5] & dat_o29) | (~block_cnt14_1 & 
   block_cnt_s[5] & dat_o29) | (~block_cnt14_1 & ~block_cnt_5[5] & block_cnt_s[5] & 
   dat_o29) | (block_cnt_5[5] & block_cnt_s[5] & dat_o29);
assign block_cnt_lm[6] = (~block_cnt14_1 & block_cnt_s[6]) | (~block_cnt14_1 & 
   ~block_cnt_5[6] & block_cnt_s[6]) | (block_cnt_5[6] & block_cnt_s[6]) | 
   (block_cnt_s[6] & ~dat_o29) | (block_cnt14_1 & block_cnt_5[6] & dat_o29) | 
   (block_cnt14_1 & block_cnt_5[6] & ~block_cnt_s[6] & dat_o29) | (~block_cnt14_1 & 
   block_cnt_s[6] & dat_o29) | (~block_cnt14_1 & ~block_cnt_5[6] & block_cnt_s[6] & 
   dat_o29) | (block_cnt_5[6] & block_cnt_s[6] & dat_o29);
assign block_cnt_lm[7] = (~block_cnt14_1 & block_cnt_s[7]) | (~block_cnt_5[6] & 
   block_cnt_s[7]) | (~block_cnt14_1 & block_cnt_5[6] & block_cnt_s[7]) | 
   (block_cnt_s[7] & ~dat_o29) | (block_cnt14_1 & ~block_cnt_5[6] & dat_o29) | 
   (block_cnt14_1 & ~block_cnt_5[6] & ~block_cnt_s[7] & dat_o29) | (~block_cnt14_1 & 
   block_cnt_s[7] & dat_o29) | (~block_cnt_5[6] & block_cnt_s[7] & dat_o29) | 
   (~block_cnt14_1 & block_cnt_5[6] & block_cnt_s[7] & dat_o29);
assign N_201_i = (block_cnt14_1 & dat_o29) | (block_cnt14_1 & dat_o29 & 
   ~enable) | (~N_259 & enable) | (~N_259 & ~dat_o29 & enable) | (~N_259 & 
   dat_o29 & enable) | (~N_259 & ~block_cnt14_1 & dat_o29 & enable) | 
   (block_cnt14_1 & dat_o29 & enable);
assign un13_ms_int_pnd_iv[0] = (ier[3] & ms_int_pnd & ~msr_read) | (ier[3] & 
   ms_int_pnd & ~ms_int_rise & ~msr_read) | (ms_int_rise & ~msr_read);
assign un10_lsr6r_0[0] = (N_259 & ~fifo_write & ~lsr6_d) | (N_259 & ~fifo_write & 
   ~lsr6_d & ~lsr6r) | (~fifo_write & lsr6r);
assign un10_lsr5r_0[0] = (~fifo_write & lsr5r) | (N_259 & ~fifo_write & 
   ~lsr6_d) | (N_259 & ~fifo_write & ~lsr5r & ~lsr6_d) | (~fifo_write & 
   lsr5r & ~lsr6_d) | (~fifo_write & lsr5r & lsr6_d);
assign un21_thre_int_pnd_iv[0] = (~dat_o31 & ~fifo_write & ~un17_thre_int_pnd_i_m_2) | 
   (~fifo_write & ~un4_thre_int_pnd_1 & ~un17_thre_int_pnd_i_m_2) | (~dat_o31 & 
   ~fifo_write & un4_thre_int_pnd_1 & ~un17_thre_int_pnd_i_m_2);
assign un30_int_o_u_0_am[0] = (~fifo_read & ~lsr_mask_condition) | (~fifo_read & 
   ~lsr_mask_condition & ~lsr_mask_d) | (~fifo_read & lsr_mask_d) | (~fifo_read & 
   ~rls_int_pnd) | (~lsr_mask_condition & rls_int_pnd) | (~lsr_mask_condition & 
   ~lsr_mask_d & rls_int_pnd) | (lsr_mask_d & rls_int_pnd);
assign un30_int_o_u_0_bm[0] = (ms_int_pnd & ~msr_read) | (ms_int_pnd & 
   ~msr_read & ~rda_int_pnd) | (rda_int_pnd) | (ms_int_pnd & ~msr_read & 
   ~thre_int_pnd) | (ms_int_pnd & ~msr_read & ~rda_int_pnd & ~thre_int_pnd) | 
   (rda_int_pnd & ~thre_int_pnd) | (thre_int_pnd);
// @9:882
  PFUMX \un30_int_o_u_0_cZ[0]  (
	.ALUT(un30_int_o_u_0_bm[0]),
	.BLUT(un30_int_o_u_0_am[0]),
	.C0(N_198),
	.Z(un30_int_o_u_0[0])
);
assign dat_o_c[0] = (N_193 & ~dat_o_2_1_0[0]) | (N_193 & ~dat_o_2_1_0[0] & 
   ~msr[0]) | (~N_193 & N_194 & msr[0]) | (N_193 & ~dat_o_2_1_0[0] & msr[0]) | 
   (N_193 & ~N_194 & ~dat_o_2_1_0[0] & msr[0]) | (N_194 & ~dat_o_2_1_0[0] & 
   msr[0]) | (~N_193 & N_194 & dat_o_2_1_0[0] & msr[0]);
assign dat_o_c[3] = (N_193 & ~dat_o_8_1_0[3]) | (N_193 & ~dat_o_8_1_0[3] & 
   ~msr[3]) | (~N_193 & N_194 & msr[3]) | (N_193 & ~dat_o_8_1_0[3] & msr[3]) | 
   (N_193 & ~N_194 & ~dat_o_8_1_0[3] & msr[3]) | (N_194 & ~dat_o_8_1_0[3] & 
   msr[3]) | (~N_193 & N_194 & dat_o_8_1_0[3] & msr[3]);
assign dat_o_c[5] = (N_193 & ~dat_o_8_1_0[5]) | (N_193 & ~dat_o_8_1_0[5] & 
   ~msr[5]) | (~N_193 & N_194 & msr[5]) | (N_193 & ~dat_o_8_1_0[5] & msr[5]) | 
   (N_193 & ~N_194 & ~dat_o_8_1_0[5] & msr[5]) | (N_194 & ~dat_o_8_1_0[5] & 
   msr[5]) | (~N_193 & N_194 & dat_o_8_1_0[5] & msr[5]);
assign dat_o_c[6] = (N_193 & ~dat_o_8_1_0[6]) | (N_193 & ~dat_o_8_1_0[6] & 
   ~msr[6]) | (~N_193 & N_194 & msr[6]) | (N_193 & ~dat_o_8_1_0[6] & msr[6]) | 
   (N_193 & ~N_194 & ~dat_o_8_1_0[6] & msr[6]) | (N_194 & ~dat_o_8_1_0[6] & 
   msr[6]) | (~N_193 & N_194 & dat_o_8_1_0[6] & msr[6]);
assign dat_o_c[4] = (N_193 & ~dat_o_8_1_0[4]) | (N_193 & ~dat_o_8_1_0[4] & 
   ~msr[4]) | (~N_193 & N_194 & msr[4]) | (N_193 & ~dat_o_8_1_0[4] & msr[4]) | 
   (N_193 & ~N_194 & ~dat_o_8_1_0[4] & msr[4]) | (N_194 & ~dat_o_8_1_0[4] & 
   msr[4]) | (~N_193 & N_194 & dat_o_8_1_0[4] & msr[4]);
assign dat_o_c[7] = (N_193 & ~dat_o_8_1_0[7]) | (N_193 & ~dat_o_8_1_0[7] & 
   ~msr[7]) | (~N_193 & N_194 & msr[7]) | (N_193 & ~dat_o_8_1_0[7] & msr[7]) | 
   (N_193 & ~N_194 & ~dat_o_8_1_0[7] & msr[7]) | (N_194 & ~dat_o_8_1_0[7] & 
   msr[7]) | (~N_193 & N_194 & dat_o_8_1_0[7] & msr[7]);
assign dat_o_7_0_am_1[3] = (~addr_i_c[1] & addr_i_c[2]) | (~addr_i_c[1] & 
   ~iir[3]) | (~addr_i_c[2] & ~iir[3]) | (~addr_i_c[1] & addr_i_c[2] & 
   ~iir[3]) | (~addr_i_c[1] & addr_i_c[2] & iir[3]) | (addr_i_c[2] & ~scratch[3]) | 
   (~iir[3] & ~scratch[3]) | (addr_i_c[2] & iir[3] & ~scratch[3]) | (~addr_i_c[1] & 
   addr_i_c[2] & scratch[3]) | (~addr_i_c[1] & ~iir[3] & scratch[3]) | 
   (~addr_i_c[2] & ~iir[3] & scratch[3]) | (~addr_i_c[1] & addr_i_c[2] & 
   ~iir[3] & scratch[3]) | (~addr_i_c[1] & addr_i_c[2] & iir[3] & scratch[3]);
assign dat_o_7_0_am_1[0] = (~addr_i_c[1] & addr_i_c[2]) | (~addr_i_c[1] & 
   ~iir[0]) | (~addr_i_c[2] & ~iir[0]) | (~addr_i_c[1] & addr_i_c[2] & 
   ~iir[0]) | (~addr_i_c[1] & addr_i_c[2] & iir[0]) | (addr_i_c[2] & ~scratch[0]) | 
   (~iir[0] & ~scratch[0]) | (addr_i_c[2] & iir[0] & ~scratch[0]) | (~addr_i_c[1] & 
   addr_i_c[2] & scratch[0]) | (~addr_i_c[1] & ~iir[0] & scratch[0]) | 
   (~addr_i_c[2] & ~iir[0] & scratch[0]) | (~addr_i_c[1] & addr_i_c[2] & 
   ~iir[0] & scratch[0]) | (~addr_i_c[1] & addr_i_c[2] & iir[0] & scratch[0]);
assign dat_o_7_0_am_1[4] = (~addr_i_c[1]) | (~scratch[4]) | (~addr_i_c[1] & 
   scratch[4]);
assign dat_o_7_0_am_1[7] = (~addr_i_c[1]) | (~scratch[7]) | (~addr_i_c[1] & 
   scratch[7]);
assign m9_e = (dl[2] & lcr[7]);
assign m17_0 = (~addr_i_c[3] & ~addr_i_c[4]);
assign dat_o_c[2] = (~N_9 & ~N_15 & m17_0) | (~N_9 & ~dat_o_sn_m7_0_a2 & 
   m17_0) | (~N_15 & dat_o_sn_m7_0_a2 & m17_0);
assign m9_e_0 = (dl[1] & lcr[7]);
assign dat_o_c[1] = (~dat_o_sn_m7_0_a2 & ~m7_0 & m17_0) | (dat_o_sn_m7_0_a2 & 
   ~m14_0 & m17_0) | (~m7_0 & ~m14_0 & m17_0) | (dat_o_sn_m7_0_a2 & m7_0 & 
   ~m14_0 & m17_0) | (~dat_o_sn_m7_0_a2 & ~m7_0 & m14_0 & m17_0);
assign N_206_i = (~lcr[6]) | (~lcr[6] & ~mcr[4]) | (mcr[4]);
// @9:785
  CCU2 un5_rda_int_cry_2_0 (
	.A0(fcr[0]),
	.B0(GND),
	.C0(GND),
	.D0(GND),
	.A1(fcr[1]),
	.B1(GND),
	.C1(GND),
	.D1(GND),
	.CIN(un5_rda_int_cry_1),
	.COUT0(un5_rda_int_cry_2),
	.COUT1(un5_rda_int_cry_4),
	.S0(un5_rda_int_cry_2_0_S0),
	.S1(un5_rda_int_cry_2_0_S1)
);
defparam un5_rda_int_cry_2_0.INIT0=16'h5001;
defparam un5_rda_int_cry_2_0.INIT1=16'h5001;
defparam un5_rda_int_cry_2_0.INJECT1_0="NO";
defparam un5_rda_int_cry_2_0.INJECT1_1="YES";
// @9:785
  CCU2 un5_rda_int_cry_0_0 (
	.A0(fcr[0]),
	.B0(fcr[1]),
	.C0(GND),
	.D0(GND),
	.A1(fcr[0]),
	.B1(fcr[1]),
	.C1(GND),
	.D1(GND),
	.CIN(GND),
	.COUT0(un5_rda_int_cry_0),
	.COUT1(un5_rda_int_cry_1),
	.S0(un5_rda_int_cry_0_0_S0),
	.S1(un5_rda_int_cry_0_0_S1)
);
defparam un5_rda_int_cry_0_0.INIT0=16'he00e;
defparam un5_rda_int_cry_0_0.INIT1=16'h7007;
defparam un5_rda_int_cry_0_0.INJECT1_0="NO";
defparam un5_rda_int_cry_0_0.INJECT1_1="NO";
// @9:729
  CCU2 dlc_5_cry_14_0 (
	.A0(N_214),
	.B0(dl[14]),
	.C0(dlc[14]),
	.D0(start_dlc),
	.A1(N_211),
	.B1(dlc[15]),
	.C1(dl[15]),
	.D1(GND),
	.CIN(dlc_5_cry_13),
	.COUT0(dlc_5_cry_14),
	.COUT1(dlc_5_cry_14_0_COUT1),
	.S0(dlc_5[14]),
	.S1(dlc_5[15])
);
defparam dlc_5_cry_14_0.INIT0=16'h3327;
defparam dlc_5_cry_14_0.INIT1=16'h5027;
defparam dlc_5_cry_14_0.INJECT1_0="YES";
defparam dlc_5_cry_14_0.INJECT1_1="NO";
// @9:729
  CCU2 dlc_5_cry_12_0 (
	.A0(N_214),
	.B0(dl[12]),
	.C0(dlc[12]),
	.D0(start_dlc),
	.A1(N_214),
	.B1(dl[13]),
	.C1(dlc[13]),
	.D1(start_dlc),
	.CIN(dlc_5_cry_11),
	.COUT0(dlc_5_cry_12),
	.COUT1(dlc_5_cry_13),
	.S0(dlc_5[12]),
	.S1(dlc_5[13])
);
defparam dlc_5_cry_12_0.INIT0=16'h3327;
defparam dlc_5_cry_12_0.INIT1=16'h3327;
defparam dlc_5_cry_12_0.INJECT1_0="YES";
defparam dlc_5_cry_12_0.INJECT1_1="YES";
// @9:729
  CCU2 dlc_5_cry_10_0 (
	.A0(N_214),
	.B0(dl[10]),
	.C0(dlc[10]),
	.D0(start_dlc),
	.A1(N_214),
	.B1(dl[11]),
	.C1(dlc[11]),
	.D1(start_dlc),
	.CIN(dlc_5_cry_9),
	.COUT0(dlc_5_cry_10),
	.COUT1(dlc_5_cry_11),
	.S0(dlc_5[10]),
	.S1(dlc_5[11])
);
defparam dlc_5_cry_10_0.INIT0=16'h3327;
defparam dlc_5_cry_10_0.INIT1=16'h3327;
defparam dlc_5_cry_10_0.INJECT1_0="YES";
defparam dlc_5_cry_10_0.INJECT1_1="YES";
// @9:729
  CCU2 dlc_5_cry_8_0 (
	.A0(N_214),
	.B0(dl[8]),
	.C0(dlc[8]),
	.D0(start_dlc),
	.A1(N_214),
	.B1(dl[9]),
	.C1(dlc[9]),
	.D1(start_dlc),
	.CIN(dlc_5_cry_7),
	.COUT0(dlc_5_cry_8),
	.COUT1(dlc_5_cry_9),
	.S0(dlc_5[8]),
	.S1(dlc_5[9])
);
defparam dlc_5_cry_8_0.INIT0=16'h3327;
defparam dlc_5_cry_8_0.INIT1=16'h3327;
defparam dlc_5_cry_8_0.INJECT1_0="YES";
defparam dlc_5_cry_8_0.INJECT1_1="YES";
// @9:729
  CCU2 dlc_5_cry_6_0 (
	.A0(N_214),
	.B0(dl[6]),
	.C0(dlc[6]),
	.D0(start_dlc),
	.A1(N_214),
	.B1(dl[7]),
	.C1(dlc[7]),
	.D1(start_dlc),
	.CIN(dlc_5_cry_5),
	.COUT0(dlc_5_cry_6),
	.COUT1(dlc_5_cry_7),
	.S0(dlc_5[6]),
	.S1(dlc_5[7])
);
defparam dlc_5_cry_6_0.INIT0=16'h3327;
defparam dlc_5_cry_6_0.INIT1=16'h3327;
defparam dlc_5_cry_6_0.INJECT1_0="YES";
defparam dlc_5_cry_6_0.INJECT1_1="YES";
// @9:729
  CCU2 dlc_5_cry_4_0 (
	.A0(N_214),
	.B0(dl[4]),
	.C0(dlc[4]),
	.D0(start_dlc),
	.A1(N_214),
	.B1(dl[5]),
	.C1(dlc[5]),
	.D1(start_dlc),
	.CIN(dlc_5_cry_3),
	.COUT0(dlc_5_cry_4),
	.COUT1(dlc_5_cry_5),
	.S0(dlc_5[4]),
	.S1(dlc_5[5])
);
defparam dlc_5_cry_4_0.INIT0=16'h3327;
defparam dlc_5_cry_4_0.INIT1=16'h3327;
defparam dlc_5_cry_4_0.INJECT1_0="YES";
defparam dlc_5_cry_4_0.INJECT1_1="YES";
// @9:729
  CCU2 dlc_5_cry_2_0 (
	.A0(N_214),
	.B0(dl[2]),
	.C0(dlc[2]),
	.D0(start_dlc),
	.A1(N_214),
	.B1(dl[3]),
	.C1(dlc[3]),
	.D1(start_dlc),
	.CIN(dlc_5_cry_1),
	.COUT0(dlc_5_cry_2),
	.COUT1(dlc_5_cry_3),
	.S0(dlc_5[2]),
	.S1(dlc_5[3])
);
defparam dlc_5_cry_2_0.INIT0=16'h3327;
defparam dlc_5_cry_2_0.INIT1=16'h3327;
defparam dlc_5_cry_2_0.INJECT1_0="YES";
defparam dlc_5_cry_2_0.INJECT1_1="YES";
// @9:729
  CCU2 dlc_5_cry_0_0 (
	.A0(N_214),
	.B0(dl[0]),
	.C0(dlc[0]),
	.D0(start_dlc),
	.A1(N_214),
	.B1(dl[1]),
	.C1(dlc[1]),
	.D1(start_dlc),
	.CIN(GND),
	.COUT0(dlc_5_cry_0),
	.COUT1(dlc_5_cry_1),
	.S0(un1_dlc_2_i[0]),
	.S1(dlc_5[1])
);
defparam dlc_5_cry_0_0.INIT0=16'h3327;
defparam dlc_5_cry_0_0.INIT1=16'h3327;
defparam dlc_5_cry_0_0.INJECT1_0="YES";
defparam dlc_5_cry_0_0.INJECT1_1="YES";
// @9:764
  CCU2 \block_cnt_cry_0[6]  (
	.A0(block_cnt[6]),
	.B0(VCC),
	.C0(GND),
	.D0(GND),
	.A1(block_cnt[7]),
	.B1(VCC),
	.C1(GND),
	.D1(GND),
	.CIN(block_cnt_cry[5]),
	.COUT0(block_cnt_cry[6]),
	.COUT1(block_cnt_cry_0_COUT1[6]),
	.S0(block_cnt_s[6]),
	.S1(block_cnt_s[7])
);
defparam \block_cnt_cry_0[6] .INIT0=16'h5006;
defparam \block_cnt_cry_0[6] .INIT1=16'h5006;
defparam \block_cnt_cry_0[6] .INJECT1_0="YES";
defparam \block_cnt_cry_0[6] .INJECT1_1="NO";
// @9:764
  CCU2 \block_cnt_cry_0[4]  (
	.A0(block_cnt[4]),
	.B0(VCC),
	.C0(GND),
	.D0(GND),
	.A1(block_cnt[5]),
	.B1(VCC),
	.C1(GND),
	.D1(GND),
	.CIN(block_cnt_cry[3]),
	.COUT0(block_cnt_cry[4]),
	.COUT1(block_cnt_cry[5]),
	.S0(block_cnt_s[4]),
	.S1(block_cnt_s[5])
);
defparam \block_cnt_cry_0[4] .INIT0=16'h5006;
defparam \block_cnt_cry_0[4] .INIT1=16'h5006;
defparam \block_cnt_cry_0[4] .INJECT1_0="YES";
defparam \block_cnt_cry_0[4] .INJECT1_1="YES";
// @9:764
  CCU2 \block_cnt_cry_0[2]  (
	.A0(block_cnt[2]),
	.B0(VCC),
	.C0(GND),
	.D0(GND),
	.A1(block_cnt[3]),
	.B1(VCC),
	.C1(GND),
	.D1(GND),
	.CIN(block_cnt_cry[1]),
	.COUT0(block_cnt_cry[2]),
	.COUT1(block_cnt_cry[3]),
	.S0(block_cnt_s[2]),
	.S1(block_cnt_s[3])
);
defparam \block_cnt_cry_0[2] .INIT0=16'h5006;
defparam \block_cnt_cry_0[2] .INIT1=16'h5006;
defparam \block_cnt_cry_0[2] .INJECT1_0="YES";
defparam \block_cnt_cry_0[2] .INJECT1_1="YES";
// @9:764
  CCU2 \block_cnt_cry_0[0]  (
	.A0(block_cnt[0]),
	.B0(VCC),
	.C0(GND),
	.D0(GND),
	.A1(block_cnt[1]),
	.B1(VCC),
	.C1(GND),
	.D1(GND),
	.CIN(GND),
	.COUT0(block_cnt_cry[0]),
	.COUT1(block_cnt_cry[1]),
	.S0(block_cnt_s[0]),
	.S1(block_cnt_s[1])
);
defparam \block_cnt_cry_0[0] .INIT0=16'h5006;
defparam \block_cnt_cry_0[0] .INIT1=16'h5006;
defparam \block_cnt_cry_0[0] .INJECT1_0="YES";
defparam \block_cnt_cry_0[0] .INJECT1_1="YES";
  assign GND_Z = 1'b0;
  assign VCC_Z = 1'b1;
endmodule /* uart_regs */