uart_regs.vm

vlsi UART referene, use UART0_3

// @9:568
  FD1P3AX \dl_Z[7]  (
	.D(dat_i_c[7]),
	.SP(dl_0_sqmuxa),
	.CK(clk_c),
	.Q(dl[7])
);
// @9:727
  FD1S3AX \dlc_Z[7]  (
	.D(dlc_5[7]),
	.CK(clk_c),
	.Q(dlc[7])
);
// @9:727
  FD1S3AX \dlc_Z[8]  (
	.D(dlc_5[8]),
	.CK(clk_c),
	.Q(dlc[8])
);
// @9:518
  FD1P3AX \dl_Z[8]  (
	.D(dat_i_c[0]),
	.SP(ier_0_sqmuxa),
	.CK(clk_c),
	.Q(dl[8])
);
// @9:727
  FD1S3AX \dlc_Z[9]  (
	.D(dlc_5[9]),
	.CK(clk_c),
	.Q(dlc[9])
);
// @9:518
  FD1P3AX \dl_Z[9]  (
	.D(dat_i_c[1]),
	.SP(ier_0_sqmuxa),
	.CK(clk_c),
	.Q(dl[9])
);
// @9:727
  FD1S3AX \dlc_Z[10]  (
	.D(dlc_5[10]),
	.CK(clk_c),
	.Q(dlc[10])
);
// @9:518
  FD1P3AX \dl_Z[10]  (
	.D(dat_i_c[2]),
	.SP(ier_0_sqmuxa),
	.CK(clk_c),
	.Q(dl[10])
);
// @9:518
  FD1P3AX \dl_Z[11]  (
	.D(dat_i_c[3]),
	.SP(ier_0_sqmuxa),
	.CK(clk_c),
	.Q(dl[11])
);
// @9:727
  FD1S3AX \dlc_Z[11]  (
	.D(dlc_5[11]),
	.CK(clk_c),
	.Q(dlc[11])
);
// @9:518
  FD1P3AX \dl_Z[12]  (
	.D(dat_i_c[4]),
	.SP(ier_0_sqmuxa),
	.CK(clk_c),
	.Q(dl[12])
);
// @9:727
  FD1S3AX \dlc_Z[12]  (
	.D(dlc_5[12]),
	.CK(clk_c),
	.Q(dlc[12])
);
// @9:727
  FD1S3AX \dlc_Z[13]  (
	.D(dlc_5[13]),
	.CK(clk_c),
	.Q(dlc[13])
);
// @9:518
  FD1P3AX \dl_Z[13]  (
	.D(dat_i_c[5]),
	.SP(ier_0_sqmuxa),
	.CK(clk_c),
	.Q(dl[13])
);
// @9:727
  FD1S3AX \dlc_Z[14]  (
	.D(dlc_5[14]),
	.CK(clk_c),
	.Q(dlc[14])
);
// @9:518
  FD1P3AX \dl_Z[14]  (
	.D(dat_i_c[6]),
	.SP(ier_0_sqmuxa),
	.CK(clk_c),
	.Q(dl[14])
);
// @9:727
  FD1S3AX \dlc_Z[15]  (
	.D(dlc_5[15]),
	.CK(clk_c),
	.Q(dlc[15])
);
// @9:518
  FD1P3AX \dl_Z[15]  (
	.D(dat_i_c[7]),
	.SP(ier_0_sqmuxa),
	.CK(clk_c),
	.Q(dl[15])
);
// @9:609
  FD1S3AX \delayed_modem_signals_Z[0]  (
	.D(modem_inputs_c_i[3]),
	.CK(clk_c),
	.Q(delayed_modem_signals[0])
);
// @9:609
  FD1S3AX \delayed_modem_signals_Z[1]  (
	.D(modem_inputs_c_i[2]),
	.CK(clk_c),
	.Q(delayed_modem_signals[1])
);
// @9:609
  FD1S3AX \delayed_modem_signals_Z[2]  (
	.D(modem_inputs_c_i[1]),
	.CK(clk_c),
	.Q(delayed_modem_signals[2])
);
// @9:609
  FD1S3AX \delayed_modem_signals_Z[3]  (
	.D(modem_inputs_c_i[0]),
	.CK(clk_c),
	.Q(delayed_modem_signals[3])
);
// @9:764
  FD1P3AX \block_cnt_Z[0]  (
	.D(block_cnt_lm[0]),
	.SP(N_201_i),
	.CK(clk_c),
	.Q(block_cnt[0])
);
// @9:764
  FD1P3AX \block_cnt_Z[1]  (
	.D(block_cnt_lm[1]),
	.SP(N_201_i),
	.CK(clk_c),
	.Q(block_cnt[1])
);
// @9:764
  FD1P3AX \block_cnt_Z[2]  (
	.D(block_cnt_lm[2]),
	.SP(N_201_i),
	.CK(clk_c),
	.Q(block_cnt[2])
);
// @9:764
  FD1P3AX \block_cnt_Z[3]  (
	.D(block_cnt_lm[3]),
	.SP(N_201_i),
	.CK(clk_c),
	.Q(block_cnt[3])
);
// @9:764
  FD1P3AX \block_cnt_Z[4]  (
	.D(block_cnt_lm[4]),
	.SP(N_201_i),
	.CK(clk_c),
	.Q(block_cnt[4])
);
// @9:764
  FD1P3AX \block_cnt_Z[5]  (
	.D(block_cnt_lm[5]),
	.SP(N_201_i),
	.CK(clk_c),
	.Q(block_cnt[5])
);
// @9:764
  FD1P3AX \block_cnt_Z[6]  (
	.D(block_cnt_lm[6]),
	.SP(N_201_i),
	.CK(clk_c),
	.Q(block_cnt[6])
);
// @9:764
  FD1P3AX \block_cnt_Z[7]  (
	.D(block_cnt_lm[7]),
	.SP(N_201_i),
	.CK(clk_c),
	.Q(block_cnt[7])
);
  GSR GSR_INST (
	.GSR(GSRN)
);
  INV GSRN_cZ (
	.A(rst_i_c),
	.Z(GSRN)
);
// @9:339
  OB int_o_pad (
	.I(int_o_c),
	.O(int_o)
);
// @9:286
  OB dtr_pad_o_pad (
	.I(mcr[0]),
	.O(dtr_pad_o)
);
// @9:285
  OB rts_pad_o_pad (
	.I(mcr[1]),
	.O(rts_pad_o)
);
// @9:281
  OB stx_pad_o_pad (
	.I(N_206_i),
	.O(stx_pad_o)
);
// @9:284
  IB \modem_inputs_pad[3]  (
	.I(modem_inputs[3]),
	.O(modem_inputs_c[3])
);
// @9:284
  IB \modem_inputs_pad[2]  (
	.I(modem_inputs[2]),
	.O(modem_inputs_c[2])
);
// @9:284
  IB \modem_inputs_pad[1]  (
	.I(modem_inputs[1]),
	.O(modem_inputs_c[1])
);
// @9:284
  IB \modem_inputs_pad[0]  (
	.I(modem_inputs[0]),
	.O(modem_inputs_c[0])
);
// @9:279
  IB re_i_pad (
	.I(re_i),
	.O(re_i_c)
);
// @9:278
  IB we_i_pad (
	.I(we_i),
	.O(we_i_c)
);
// @9:320
  OB \dat_o_pad[7]  (
	.I(dat_o_c[7]),
	.O(dat_o[7])
);
// @9:320
  OB \dat_o_pad[6]  (
	.I(dat_o_c[6]),
	.O(dat_o[6])
);
// @9:320
  OB \dat_o_pad[5]  (
	.I(dat_o_c[5]),
	.O(dat_o[5])
);
// @9:320
  OB \dat_o_pad[4]  (
	.I(dat_o_c[4]),
	.O(dat_o[4])
);
// @9:320
  OB \dat_o_pad[3]  (
	.I(dat_o_c[3]),
	.O(dat_o[3])
);
// @9:320
  OB \dat_o_pad[2]  (
	.I(dat_o_c[2]),
	.O(dat_o[2])
);
// @9:320
  OB \dat_o_pad[1]  (
	.I(dat_o_c[1]),
	.O(dat_o[1])
);
// @9:320
  OB \dat_o_pad[0]  (
	.I(dat_o_c[0]),
	.O(dat_o[0])
);
// @9:276
  IB \dat_i_pad[7]  (
	.I(dat_i[7]),
	.O(dat_i_c[7])
);
// @9:276
  IB \dat_i_pad[6]  (
	.I(dat_i[6]),
	.O(dat_i_c[6])
);
// @9:276
  IB \dat_i_pad[5]  (
	.I(dat_i[5]),
	.O(dat_i_c[5])
);
// @9:276
  IB \dat_i_pad[4]  (
	.I(dat_i[4]),
	.O(dat_i_c[4])
);
// @9:276
  IB \dat_i_pad[3]  (
	.I(dat_i[3]),
	.O(dat_i_c[3])
);
// @9:276
  IB \dat_i_pad[2]  (
	.I(dat_i[2]),
	.O(dat_i_c[2])
);
// @9:276
  IB \dat_i_pad[1]  (
	.I(dat_i[1]),
	.O(dat_i_c[1])
);
// @9:276
  IB \dat_i_pad[0]  (
	.I(dat_i[0]),
	.O(dat_i_c[0])
);
// @9:275
  IB \addr_i_pad[4]  (
	.I(addr_i[4]),
	.O(addr_i_c[4])
);
// @9:275
  IB \addr_i_pad[3]  (
	.I(addr_i[3]),
	.O(addr_i_c[3])
);
// @9:275
  IB \addr_i_pad[2]  (
	.I(addr_i[2]),
	.O(addr_i_c[2])
);
// @9:275
  IB \addr_i_pad[1]  (
	.I(addr_i[1]),
	.O(addr_i_c[1])
);
// @9:275
  IB \addr_i_pad[0]  (
	.I(addr_i[0]),
	.O(addr_i_c[0])
);
// @9:274
  IB rst_i_pad (
	.I(rst_i),
	.O(rst_i_c)
);
// @9:273
  IB clk_pad (
	.I(clk),
	.O(clk_c)
);
assign lcr6_1 = (addr_i_c[1] & ~addr_i_c[2]);
assign dat_o_sn_m7_0_a2 = (~addr_i_c[1] & ~addr_i_c[2]);
assign rda_int = (ier[0] & ~un5_rda_int_cry_4);
assign thre_int = (ier[1] & lsr5r);
assign un2_ms_int_0 = (~msr[2] & ~msr[3]);
assign un1_thre_set_en_0 = (~block_cnt[2] & ~block_cnt[3]);
assign un1_dl_0 = (~dl[4] & ~dl[5]);
assign N_57 = (dl[8] & ier[0]) | (ier[0] & ~lcr[7]) | (dl[8] & lcr[7]);
assign N_35 = (~addr_i_c[1] & lsr5r) | (~addr_i_c[1] & lsr5r & ~scratch[5]) | 
   (addr_i_c[1] & scratch[5]) | (addr_i_c[1] & ~lsr5r & scratch[5]) | 
   (lsr5r & scratch[5]);
assign un7_dcd_c_0[3] = (mcr[1] & mcr[4]) | (mcr[1] & mcr[4] & ~modem_inputs_c[3]) | 
   (mcr[1] & modem_inputs_c[3]) | (~mcr[4] & modem_inputs_c[3]) | (mcr[1] & 
   mcr[4] & modem_inputs_c[3]);
assign un7_dcd_c_0[2] = (mcr[0] & mcr[4]) | (mcr[0] & mcr[4] & ~modem_inputs_c[2]) | 
   (mcr[0] & modem_inputs_c[2]) | (~mcr[4] & modem_inputs_c[2]) | (mcr[0] & 
   mcr[4] & modem_inputs_c[2]);
assign un7_dcd_c_0[1] = (mcr[2] & mcr[4]) | (mcr[2] & mcr[4] & ~modem_inputs_c[1]) | 
   (mcr[2] & modem_inputs_c[1]) | (~mcr[4] & modem_inputs_c[1]) | (mcr[2] & 
   mcr[4] & modem_inputs_c[1]);
assign un7_dcd_c_0[0] = (mcr[3] & mcr[4]) | (mcr[3] & mcr[4] & ~modem_inputs_c[0]) | 
   (mcr[3] & modem_inputs_c[0]) | (~mcr[4] & modem_inputs_c[0]) | (mcr[3] & 
   mcr[4] & modem_inputs_c[0]);
assign N_36 = (~addr_i_c[1] & lsr6r) | (~addr_i_c[1] & lsr6r & ~scratch[6]) | 
   (addr_i_c[1] & scratch[6]) | (addr_i_c[1] & ~lsr6r & scratch[6]) | 
   (lsr6r & scratch[6]);
assign dat_o_3_0[3] = (dl[11] & ier[3]) | (ier[3] & ~lcr[7]) | (dl[11] & 
   lcr[7]);
assign dl15_1 = (~addr_i_c[1] & ~addr_i_c[2] & ~addr_i_c[3] & ~addr_i_c[4]);
assign N_193 = (addr_i_c[0] & ~addr_i_c[3] & ~addr_i_c[4]) | (~addr_i_c[2] & 
   ~addr_i_c[3] & ~addr_i_c[4]) | (addr_i_c[0] & addr_i_c[2] & ~addr_i_c[3] & 
   ~addr_i_c[4]);
assign N_194 = (addr_i_c[1] & ~addr_i_c[3] & ~addr_i_c[4]);
assign mcr8_2 = (~addr_i_c[0] & addr_i_c[2] & ~addr_i_c[3] & ~addr_i_c[4]);
assign N_198 = (~iir67_sn & ~rls_int_pnd) | (~iir67_sn & ~rda_int_pnd & 
   ~rls_int_pnd) | (rda_int_pnd & ~rls_int_pnd);
assign N_208_1 = (~ier[0] & ~rls_int_pnd) | (~ier[0] & ~rls_int_pnd & ~un5_rda_int_cry_4) | 
   (~rls_int_pnd & un5_rda_int_cry_4);
assign lcr6_2 = (addr_i_c[0] & ~addr_i_c[3] & ~addr_i_c[4] & we_i_c);
assign block_cnt_5[4] = (~lcr[0] & ~lcr[2] & ~lcr[3]) | (lcr[0] & lcr[2] & 
   ~lcr[3]) | (lcr[0] & ~lcr[2] & lcr[3]) | (~lcr[0] & lcr[2] & lcr[3]);
assign m2 = (~lcr[0] & ~lcr[1] & lcr[2]);
assign un1_thre_set_en_4 = (~block_cnt[4] & ~block_cnt[5] & ~block_cnt[6] & 
   ~block_cnt[7]);
assign un1_dl_8 = (~dl[8] & ~dl[9] & ~dl[10] & ~dl[11]);
assign un1_dl_9 = (~dl[12] & ~dl[13] & ~dl[14] & ~dl[15]);
assign un1_dl_10 = (~dl[0] & ~dl[1] & ~dl[2] & ~dl[3]);
assign un1_dlc_8 = (~dlc[8] & ~dlc[9] & ~dlc[10] & ~dlc[11]);
assign un1_dlc_9 = (~dlc[12] & ~dlc[13] & ~dlc[14] & ~dlc[15]);
assign un1_dlc_10 = (~dlc[0] & ~dlc[1] & ~dlc[2] & ~dlc[3]);
assign un1_dlc_11 = (~dlc[4] & ~dlc[5] & ~dlc[6] & ~dlc[7]);
assign lsr_mask_condition_2 = (~addr_i_c[3] & ~addr_i_c[4] & ~lcr[7] & 
   re_i_c);
assign un4_thre_int_pnd_1 = (iir[1] & ~iir[2] & ~lcr[7] & re_i_c);
assign block_cnt14_1 = (~lcr[7] & lsr5r & we_i_c);
assign ms_int = (ier[3] & msr[0]) | (ier[3] & msr[0] & ~msr[1]) | (ier[3] & 
   msr[1]) | (ier[3] & ~un2_ms_int_0) | (ier[3] & msr[0] & un2_ms_int_0) | 
   (ier[3] & msr[0] & ~msr[1] & un2_ms_int_0) | (ier[3] & msr[1] & un2_ms_int_0);
assign msr_4[3] = (~delayed_modem_signals[3] & ~modem_inputs_c[0] & ~msi_reset) | 
   (delayed_modem_signals[3] & modem_inputs_c[0] & ~msi_reset) | (~delayed_modem_signals[3] & 
   ~modem_inputs_c[0] & ~msi_reset & ~msr[3]) | (delayed_modem_signals[3] & 
   modem_inputs_c[0] & ~msi_reset & ~msr[3]) | (~msi_reset & msr[3]);
assign msr_4[2] = (~delayed_modem_signals[2] & ~modem_inputs_c[1] & ~msi_reset) | 
   (delayed_modem_signals[2] & modem_inputs_c[1] & ~msi_reset) | (~delayed_modem_signals[2] & 
   ~modem_inputs_c[1] & ~msi_reset & ~msr[2]) | (delayed_modem_signals[2] & 
   modem_inputs_c[1] & ~msi_reset & ~msr[2]) | (~msi_reset & msr[2]);
assign msr_4[1] = (~delayed_modem_signals[1] & ~modem_inputs_c[2] & ~msi_reset) | 
   (delayed_modem_signals[1] & modem_inputs_c[2] & ~msi_reset) | (~delayed_modem_signals[1] & 
   ~modem_inputs_c[2] & ~msi_reset & ~msr[1]) | (delayed_modem_signals[1] & 
   modem_inputs_c[2] & ~msi_reset & ~msr[1]) | (~msi_reset & msr[1]);
assign msr_4[0] = (~delayed_modem_signals[0] & ~modem_inputs_c[3] & ~msi_reset) | 
   (delayed_modem_signals[0] & modem_inputs_c[3] & ~msi_reset) | (~delayed_modem_signals[0] & 
   ~modem_inputs_c[3] & ~msi_reset & ~msr[0]) | (delayed_modem_signals[0] & 
   modem_inputs_c[3] & ~msi_reset & ~msr[0]) | (~msi_reset & msr[0]);
assign un17_thre_int_pnd_i_m_2 = (~ier[1]) | (~ier[1] & ~thre_int_pnd) | 
   (~lsr5r & ~thre_int_pnd) | (~ier[1] & lsr5r & ~thre_int_pnd) | (~ier[1] & 
   ~thre_int_d & ~thre_int_pnd) | (~lsr5r & ~thre_int_d & ~thre_int_pnd) | 
   (~ier[1] & lsr5r & ~thre_int_d & ~thre_int_pnd) | (thre_int_d & ~thre_int_pnd) | 
   (~ier[1] & thre_int_pnd);
assign iir67 = (~ier[0] & iir67_sn & ~rls_int_pnd) | (~ier[0] & iir67_sn & 
   ~rls_int_pnd & ~un5_rda_int_cry_4) | (iir67_sn & ~rls_int_pnd & un5_rda_int_cry_4);
assign dat_o29 = (dat_o_sn_m7_0_a2 & ~addr_i_c[0] & ~addr_i_c[3] & ~addr_i_c[4]);
assign dat_o31 = (~addr_i_c[0] & ~addr_i_c[3] & ~addr_i_c[4] & lcr6_1);
assign scratch7 = (addr_i_c[1] & addr_i_c[2] & lcr6_2);
assign lsr_mask_condition = (addr_i_c[0] & ~addr_i_c[1] & addr_i_c[2] & 
   lsr_mask_condition_2);
assign msr_read = (addr_i_c[1] & ~lcr[7] & mcr8_2 & re_i_c);