uart_regs.vm

vlsi UART referene, use UART0_3

//
// Written by Synplify
// Product Version "Version 8.8L2"
// Program "Synplify", Mapper "8.8.0, Build 018R"
// Sat Mar 07 01:35:09 2009
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\c:\isptools7_0\synpbase\lib\lucent\xp.v "
// file 2 "\c:\isptools7_0\ispcpld\..\cae_library\synthesis\verilog\xp.v "
// file 3 "\f:\new_uart\uart0_2\uart0_3\uart_3.h "
// file 4 "\f:\new_uart\uart0_2\uart0_3\uart_receiver.v "
// file 5 "\f:\new_uart\uart0_2\uart0_3\uart_defines.v "
// file 6 "\f:\new_uart\uart0_2\uart0_3\uart_sync_flops.v "
// file 7 "\f:\new_uart\uart0_2\uart0_3\timescale.v "
// file 8 "\f:\new_uart\uart0_2\uart0_3\uart_transmitter.v "
// file 9 "\f:\new_uart\uart0_2\uart0_3\uart_regs.v "

`timescale 100 ps/100 ps
module uart_regs (
  clk,
  rst_i,
  addr_i,
  dat_i,
  dat_o,
  we_i,
  re_i,
  modem_inputs,
  stx_pad_o,
  srx_pad_i,
  rts_pad_o,
  dtr_pad_o,
  int_o
)
;
input clk ;
input rst_i ;
input [4:0] addr_i ;
input [7:0] dat_i ;
output [7:0] dat_o ;
input we_i ;
input re_i ;
input [3:0] modem_inputs ;
output stx_pad_o ;
input srx_pad_i ;
output rts_pad_o ;
output dtr_pad_o ;
output int_o ;
wire clk ;
wire rst_i ;
wire we_i ;
wire re_i ;
wire stx_pad_o ;
wire srx_pad_i ;
wire rts_pad_o ;
wire dtr_pad_o ;
wire int_o ;
wire [7:0] lcr;
wire [1:0] fcr;
wire [3:0] iir;
wire [4:0] mcr;
wire [3:0] ier;
wire [3:0] delayed_modem_signals;
wire [3:0] un7_dcd_c_0;
wire [7:0] msr;
wire [7:0] block_cnt;
wire [15:0] dlc;
wire [7:0] scratch;
wire [15:0] dl;
wire [3:0] msr_4;
wire [0:0] un10_lsr5r_0;
wire [0:0] un10_lsr6r_0;
wire [15:1] dlc_5;
wire [6:4] block_cnt_5;
wire [0:0] un30_int_o_u_0;
wire [3:3] dat_o_3_0;
wire [0:0] un21_thre_int_pnd_iv;
wire [0:0] un13_ti_int_pnd_iv;
wire [0:0] un13_ms_int_pnd_iv;
wire [0:0] un13_rls_int_pnd_iv;
wire [0:0] un1_dlc_2_i;
wire [6:0] block_cnt_cry;
wire [7:0] block_cnt_s;
wire [7:0] block_cnt_lm;
wire [6:6] block_cnt_cry_0_COUT1;
wire [0:0] un30_int_o_u_0_am;
wire [0:0] un30_int_o_u_0_bm;
wire [0:0] dat_o_2_1_0;
wire [7:3] dat_o_8_1_0;
wire [7:0] dat_o_7_0_am_1;
wire [4:0] addr_i_c;
wire [7:0] dat_i_c;
wire [7:0] dat_o_c;
wire [3:0] modem_inputs_c;
wire [7:0] block_cnt_QN;
wire [3:0] delayed_modem_signals_QN;
wire [15:0] dl_QN;
wire [15:0] dlc_QN;
wire [1:0] fcr_QN;
wire [3:0] ier_QN;
wire [3:0] iir_QN;
wire [7:0] lcr_QN;
wire [4:0] mcr_QN;
wire [7:0] msr_QN;
wire [7:0] scratch_QN;
wire [3:0] modem_inputs_c_i;
wire [7:3] dat_o_8_1_0_am;
wire [7:3] dat_o_8_1_0_bm;
wire [0:0] dat_o_2_1_0_am;
wire [0:0] dat_o_2_1_0_bm;
wire enable ;
wire lsr_mask_d ;
wire msi_reset ;
wire lsr6_d ;
wire rda_int_d ;
wire thre_int_d ;
wire ms_int_d ;
wire rls_int_pnd ;
wire rda_int_pnd ;
wire thre_int_pnd ;
wire ms_int_pnd ;
wire iir67_sn ;
wire thre_int ;
wire lsr5r ;
wire mcr8 ;
wire lsr_mask_condition ;
wire fifo_write ;
wire lcr6 ;
wire tx_reset11 ;
wire scratch7 ;
wire dl_0_sqmuxa ;
wire ms_int ;
wire start_dlc ;
wire msi_reset13 ;
wire ier_0_sqmuxa ;
wire ier_1_sqmuxa ;
wire enable10 ;
wire rda_int ;
wire lsr6r ;
wire iir67 ;
wire un1_rda_int_1_0 ;
wire m2 ;
wire dat_o_sn_m7_0_a2 ;
wire un5_rda_int_cry_0 ;
wire un5_rda_int_cry_1 ;
wire un5_rda_int_cry_2 ;
wire un5_rda_int_cry_4 ;
wire N_214 ;
wire dat_o31 ;
wire fifo_read ;
wire lcr6_1 ;
wire lcr6_2 ;
wire dat_o29 ;
wire msr_read ;
wire N_36 ;
wire N_193 ;
wire N_194 ;
wire N_35 ;
wire dl15_1 ;
wire N_259 ;
wire N_278 ;
wire N_280 ;
wire N_281 ;
wire N_206_i ;
wire N_282 ;
wire N_283 ;
wire N_284 ;
wire N_285 ;
wire N_286 ;
wire N_287 ;
wire mcr8_2 ;
wire N_57 ;
wire ms_int_rise ;
wire N_198 ;
wire un17_thre_int_pnd_i_m_2 ;
wire N_208_1 ;
wire dlc_5_cry_0 ;
wire dlc_5_cry_1 ;
wire dlc_5_cry_2 ;
wire dlc_5_cry_3 ;
wire dlc_5_cry_4 ;
wire dlc_5_cry_5 ;
wire dlc_5_cry_6 ;
wire dlc_5_cry_7 ;
wire dlc_5_cry_8 ;
wire dlc_5_cry_9 ;
wire dlc_5_cry_10 ;
wire dlc_5_cry_11 ;
wire dlc_5_cry_12 ;
wire dlc_5_cry_13 ;
wire dlc_5_cry_14 ;
wire N_211 ;
wire un13_rda_int_pnd_i_m_i ;
wire N_208_i ;
wire N_192_i ;
wire N_201_i ;
wire N_581 ;
wire N_582 ;
wire N_583 ;
wire N_584 ;
wire un2_ms_int_0 ;
wire un1_thre_set_en_0 ;
wire un1_thre_set_en_4 ;
wire un1_dl_0 ;
wire un1_dl_8 ;
wire un1_dl_9 ;
wire un1_dl_10 ;
wire un1_dl_12 ;
wire un1_dlc_8 ;
wire un1_dlc_9 ;
wire un1_dlc_10 ;
wire un1_dlc_11 ;
wire un1_dlc_12 ;
wire lsr_mask_condition_2 ;
wire un4_thre_int_pnd_1 ;
wire block_cnt14_1 ;
wire un5_rda_int_cry_0_0_S0 ;
wire dlc_5_cry_14_0_COUT1 ;
wire un5_rda_int_cry_0_0_S1 ;
wire un5_rda_int_cry_2_0_S0 ;
wire un5_rda_int_cry_2_0_S1 ;
wire N_9 ;
wire m9_e ;
wire N_15 ;
wire m17_0 ;
wire m7_0 ;
wire m9_e_0 ;
wire m14_0 ;
wire GND ;
wire VCC ;
wire clk_c ;
wire rst_i_c ;
wire we_i_c ;
wire re_i_c ;
wire int_o_c ;
wire GSRN ;
wire enable_QN ;
wire lsr5_d_QN ;
wire lsr5r_QN ;
wire lsr6r_QN ;
wire lsr_mask_d_QN ;
wire ms_int_d_QN ;
wire ms_int_pnd_QN ;
wire msi_reset_QN ;
wire rda_int_d_QN ;
wire rda_int_pnd_QN ;
wire rls_int_pnd_QN ;
wire start_dlc_QN ;
wire thre_int_d_QN ;
wire thre_int_pnd_QN ;
wire ti_int_pnd_QN ;
wire m7_am ;
wire m7_bm ;
wire m7_0_am ;
wire m7_0_bm ;
wire m14_am ;
wire m14_bm ;
wire m14_0_am ;
wire m14_0_bm ;
wire GND_Z ;
wire VCC_Z ;
// @9:402
  PUR PUR_INST (
	.PUR(VCC)
);
  VHI VCC_0 (
	.Z(VCC)
);
  VLO GND_0 (
	.Z(GND)
);
// @9:402
  INV \modem_inputs_c_i_cZ[0]  (
	.A(modem_inputs_c[0]),
	.Z(modem_inputs_c_i[0])
);
// @9:402
  INV \modem_inputs_c_i_cZ[1]  (
	.A(modem_inputs_c[1]),
	.Z(modem_inputs_c_i[1])
);
// @9:402
  INV \modem_inputs_c_i_cZ[2]  (
	.A(modem_inputs_c[2]),
	.Z(modem_inputs_c_i[2])
);
// @9:402
  INV \modem_inputs_c_i_cZ[3]  (
	.A(modem_inputs_c[3]),
	.Z(modem_inputs_c_i[3])
);
assign lcr6 = (lcr6_2 & ~addr_i_c[2] & addr_i_c[1]);
  PFUMX m14_0_cZ (
	.ALUT(m14_0_bm),
	.BLUT(m14_0_am),
	.C0(addr_i_c[0]),
	.Z(m14_0)
);
assign m14_0_bm = (~lcr[7] & ~ier[1]) | (lcr[7] & ~dl[9]) | (~ier[1] & 
   ~dl[9]) | (lcr[7] & ier[1] & ~dl[9]) | (~lcr[7] & ~ier[1] & dl[9]);
assign m14_0_am = (~msr[1] & addr_i_c[2]) | (addr_i_c[2] & ~addr_i_c[1]) | 
   (~msr[1] & addr_i_c[2] & addr_i_c[1]) | (~msr[1] & ~m9_e_0) | (~addr_i_c[2] & 
   ~m9_e_0) | (~msr[1] & addr_i_c[2] & ~m9_e_0) | (~addr_i_c[1] & ~m9_e_0) | 
   (~msr[1] & addr_i_c[1] & ~m9_e_0) | (~addr_i_c[2] & addr_i_c[1] & ~m9_e_0) | 
   (~msr[1] & addr_i_c[2] & addr_i_c[1] & ~m9_e_0) | (~msr[1] & addr_i_c[2] & 
   m9_e_0) | (addr_i_c[2] & ~addr_i_c[1] & m9_e_0) | (~msr[1] & addr_i_c[2] & 
   addr_i_c[1] & m9_e_0);
  PFUMX m14 (
	.ALUT(m14_bm),
	.BLUT(m14_am),
	.C0(addr_i_c[0]),
	.Z(N_15)
);
assign m14_bm = (~lcr[7] & ~ier[2]) | (lcr[7] & ~dl[10]) | (~ier[2] & ~dl[10]) | 
   (lcr[7] & ier[2] & ~dl[10]) | (~lcr[7] & ~ier[2] & dl[10]);
assign m14_am = (~msr[2] & addr_i_c[2]) | (addr_i_c[2] & ~addr_i_c[1]) | 
   (~msr[2] & addr_i_c[2] & addr_i_c[1]) | (~msr[2] & ~m9_e) | (~addr_i_c[2] & 
   ~m9_e) | (~msr[2] & addr_i_c[2] & ~m9_e) | (~addr_i_c[1] & ~m9_e) | 
   (~msr[2] & addr_i_c[1] & ~m9_e) | (~addr_i_c[2] & addr_i_c[1] & ~m9_e) | 
   (~msr[2] & addr_i_c[2] & addr_i_c[1] & ~m9_e) | (~msr[2] & addr_i_c[2] & 
   m9_e) | (addr_i_c[2] & ~addr_i_c[1] & m9_e) | (~msr[2] & addr_i_c[2] & 
   addr_i_c[1] & m9_e);
// @9:442
  PFUMX \dat_o_8_1_0_cZ[6]  (
	.ALUT(dat_o_8_1_0_bm[6]),
	.BLUT(dat_o_8_1_0_am[6]),
	.C0(dat_o_sn_m7_0_a2),
	.Z(dat_o_8_1_0[6])
);
assign dat_o_8_1_0_bm[6] = (~lcr[7]) | (~lcr[7] & ~dl[6]) | (~dl[14] & 
   ~dl[6]) | (~lcr[7] & dl[14] & ~dl[6]) | (~lcr[7] & dl[6]) | (~lcr[7] & 
   ~addr_i_c[0]) | (~dl[6] & ~addr_i_c[0]) | (~lcr[7] & dl[6] & ~addr_i_c[0]) | 
   (~lcr[7] & addr_i_c[0]) | (~dl[14] & addr_i_c[0]) | (~lcr[7] & dl[14] & 
   addr_i_c[0]);
assign dat_o_8_1_0_am[6] = (addr_i_c[0] & ~lcr[6] & ~addr_i_c[2]) | (addr_i_c[0] & 
   ~lcr[6] & ~N_36) | (addr_i_c[0] & ~lcr[6] & ~addr_i_c[2] & ~N_36) | 
   (addr_i_c[2] & ~N_36) | (addr_i_c[0] & ~lcr[6] & ~addr_i_c[2] & N_36);
// @9:442
  PFUMX \dat_o_8_1_0_cZ[5]  (
	.ALUT(dat_o_8_1_0_bm[5]),
	.BLUT(dat_o_8_1_0_am[5]),
	.C0(dat_o_sn_m7_0_a2),
	.Z(dat_o_8_1_0[5])
);
assign dat_o_8_1_0_bm[5] = (~lcr[7]) | (~lcr[7] & ~dl[5]) | (~dl[13] & 
   ~dl[5]) | (~lcr[7] & dl[13] & ~dl[5]) | (~lcr[7] & dl[5]) | (~lcr[7] & 
   ~addr_i_c[0]) | (~dl[5] & ~addr_i_c[0]) | (~lcr[7] & dl[5] & ~addr_i_c[0]) | 
   (~lcr[7] & addr_i_c[0]) | (~dl[13] & addr_i_c[0]) | (~lcr[7] & dl[13] & 
   addr_i_c[0]);
assign dat_o_8_1_0_am[5] = (~addr_i_c[0] & ~addr_i_c[2]) | (~lcr[5] & ~addr_i_c[2]) | 
   (~addr_i_c[0] & lcr[5] & ~addr_i_c[2]) | (~addr_i_c[0] & ~N_35) | (~lcr[5] & 
   ~N_35) | (~addr_i_c[0] & lcr[5] & ~N_35) | (~addr_i_c[0] & ~addr_i_c[2] & 
   ~N_35) | (~lcr[5] & ~addr_i_c[2] & ~N_35) | (~addr_i_c[0] & lcr[5] & 
   ~addr_i_c[2] & ~N_35) | (addr_i_c[2] & ~N_35) | (~addr_i_c[0] & ~addr_i_c[2] & 
   N_35) | (~lcr[5] & ~addr_i_c[2] & N_35) | (~addr_i_c[0] & lcr[5] & 
   ~addr_i_c[2] & N_35);
// @9:442
  PFUMX \dat_o_8_1_0_cZ[3]  (
	.ALUT(dat_o_8_1_0_bm[3]),
	.BLUT(dat_o_8_1_0_am[3]),
	.C0(dat_o_sn_m7_0_a2),
	.Z(dat_o_8_1_0[3])
);
assign dat_o_8_1_0_bm[3] = (~lcr[7] & ~addr_i_c[0]) | (~dl[3] & ~addr_i_c[0]) | 
   (~lcr[7] & dl[3] & ~addr_i_c[0]) | (~lcr[7] & ~dat_o_3_0[3]) | (~dl[3] & 
   ~dat_o_3_0[3]) | (~lcr[7] & dl[3] & ~dat_o_3_0[3]) | (~lcr[7] & ~addr_i_c[0] & 
   ~dat_o_3_0[3]) | (~dl[3] & ~addr_i_c[0] & ~dat_o_3_0[3]) | (~lcr[7] & 
   dl[3] & ~addr_i_c[0] & ~dat_o_3_0[3]) | (addr_i_c[0] & ~dat_o_3_0[3]) | 
   (~lcr[7] & ~addr_i_c[0] & dat_o_3_0[3]) | (~dl[3] & ~addr_i_c[0] & 
   dat_o_3_0[3]) | (~lcr[7] & dl[3] & ~addr_i_c[0] & dat_o_3_0[3]);
assign dat_o_8_1_0_am[3] = (~addr_i_c[0] & dat_o_7_0_am_1[3]) | (~lcr[3] & 
   dat_o_7_0_am_1[3]) | (~addr_i_c[0] & lcr[3] & dat_o_7_0_am_1[3]) | 
   (addr_i_c[0] & ~lcr[3] & ~addr_i_c[2]) | (addr_i_c[0] & ~lcr[3] & ~dat_o_7_0_am_1[3] & 
   ~addr_i_c[2]) | (~addr_i_c[0] & dat_o_7_0_am_1[3] & ~addr_i_c[2]) | 
   (~lcr[3] & dat_o_7_0_am_1[3] & ~addr_i_c[2]) | (~addr_i_c[0] & lcr[3] & 
   dat_o_7_0_am_1[3] & ~addr_i_c[2]) | (dat_o_7_0_am_1[3] & addr_i_c[2]);
// @9:442
  PFUMX \dat_o_2_1_0_cZ[0]  (
	.ALUT(dat_o_2_1_0_bm[0]),
	.BLUT(dat_o_2_1_0_am[0]),
	.C0(dat_o_sn_m7_0_a2),
	.Z(dat_o_2_1_0[0])
);
assign dat_o_2_1_0_bm[0] = (~lcr[7] & ~addr_i_c[0]) | (~dl[0] & ~addr_i_c[0]) | 
   (~lcr[7] & dl[0] & ~addr_i_c[0]) | (~lcr[7] & ~N_57) | (~dl[0] & ~N_57) | 
   (~lcr[7] & dl[0] & ~N_57) | (~lcr[7] & ~addr_i_c[0] & ~N_57) | (~dl[0] & 
   ~addr_i_c[0] & ~N_57) | (~lcr[7] & dl[0] & ~addr_i_c[0] & ~N_57) | 
   (addr_i_c[0] & ~N_57) | (~lcr[7] & ~addr_i_c[0] & N_57) | (~dl[0] & 
   ~addr_i_c[0] & N_57) | (~lcr[7] & dl[0] & ~addr_i_c[0] & N_57);
assign dat_o_2_1_0_am[0] = (~addr_i_c[0] & dat_o_7_0_am_1[0]) | (~lcr[0] & 
   dat_o_7_0_am_1[0]) | (~addr_i_c[0] & lcr[0] & dat_o_7_0_am_1[0]) | 
   (addr_i_c[0] & ~lcr[0] & ~addr_i_c[2]) | (addr_i_c[0] & ~lcr[0] & ~dat_o_7_0_am_1[0] & 
   ~addr_i_c[2]) | (~addr_i_c[0] & dat_o_7_0_am_1[0] & ~addr_i_c[2]) | 
   (~lcr[0] & dat_o_7_0_am_1[0] & ~addr_i_c[2]) | (~addr_i_c[0] & lcr[0] & 
   dat_o_7_0_am_1[0] & ~addr_i_c[2]) | (dat_o_7_0_am_1[0] & addr_i_c[2]);
  PFUMX m7_0_cZ (
	.ALUT(m7_0_bm),
	.BLUT(m7_0_am),
	.C0(addr_i_c[0]),
	.Z(m7_0)
);
assign m7_0_bm = (~scratch[1] & ~lcr[1]) | (~lcr[1] & ~addr_i_c[2]) | (~scratch[1] & 
   addr_i_c[2]) | (~lcr[1] & ~addr_i_c[1]) | (~lcr[1] & ~addr_i_c[2] & 
   ~addr_i_c[1]) | (addr_i_c[2] & ~addr_i_c[1]) | (~scratch[1] & ~lcr[1] & 
   addr_i_c[1]) | (~lcr[1] & ~addr_i_c[2] & addr_i_c[1]) | (~scratch[1] & 
   addr_i_c[2] & addr_i_c[1]);
assign m7_0_am = (addr_i_c[2] & ~addr_i_c[1]) | (addr_i_c[2] & ~msr[1]) | 
   (addr_i_c[2] & ~addr_i_c[1] & msr[1]) | (~addr_i_c[2] & ~iir[1]) | 
   (~addr_i_c[1] & ~iir[1]) | (~addr_i_c[2] & addr_i_c[1] & ~iir[1]) | 
   (~msr[1] & ~iir[1]) | (~addr_i_c[2] & msr[1] & ~iir[1]) | (~addr_i_c[1] & 
   msr[1] & ~iir[1]) | (~addr_i_c[2] & addr_i_c[1] & msr[1] & ~iir[1]) | 
   (addr_i_c[2] & ~addr_i_c[1] & iir[1]) | (addr_i_c[2] & ~msr[1] & iir[1]) | 
   (addr_i_c[2] & ~addr_i_c[1] & msr[1] & iir[1]);
  PFUMX m7 (
	.ALUT(m7_bm),
	.BLUT(m7_am),
	.C0(addr_i_c[0]),
	.Z(N_9)
);
assign m7_bm = (addr_i_c[2] & ~addr_i_c[1]) | (addr_i_c[2] & ~scratch[2]) | 
   (addr_i_c[2] & ~addr_i_c[1] & scratch[2]) | (~addr_i_c[2] & ~lcr[2]) | 
   (~addr_i_c[1] & ~lcr[2]) | (~addr_i_c[2] & addr_i_c[1] & ~lcr[2]) | 
   (~scratch[2] & ~lcr[2]) | (~addr_i_c[2] & scratch[2] & ~lcr[2]) | (~addr_i_c[1] & 
   scratch[2] & ~lcr[2]) | (~addr_i_c[2] & addr_i_c[1] & scratch[2] & 
   ~lcr[2]) | (addr_i_c[2] & ~addr_i_c[1] & lcr[2]) | (addr_i_c[2] & ~scratch[2] & 
   lcr[2]) | (addr_i_c[2] & ~addr_i_c[1] & scratch[2] & lcr[2]);
assign m7_am = (~msr[2] & ~iir[2]) | (~iir[2] & ~addr_i_c[2]) | (~msr[2] & 
   addr_i_c[2]) | (~iir[2] & ~addr_i_c[1]) | (~iir[2] & ~addr_i_c[2] & 
   ~addr_i_c[1]) | (addr_i_c[2] & ~addr_i_c[1]) | (~msr[2] & ~iir[2] & 
   addr_i_c[1]) | (~iir[2] & ~addr_i_c[2] & addr_i_c[1]) | (~msr[2] & 
   addr_i_c[2] & addr_i_c[1]);
// @9:442
  PFUMX \dat_o_8_1_0_cZ[7]  (
	.ALUT(dat_o_8_1_0_bm[7]),
	.BLUT(dat_o_8_1_0_am[7]),
	.C0(dat_o_sn_m7_0_a2),
	.Z(dat_o_8_1_0[7])
);
assign dat_o_8_1_0_bm[7] = (~lcr[7]) | (~lcr[7] & ~dl[7]) | (~dl[15] & 
   ~dl[7]) | (~lcr[7] & dl[15] & ~dl[7]) | (~lcr[7] & dl[7]) | (~lcr[7] & 
   ~addr_i_c[0]) | (~dl[7] & ~addr_i_c[0]) | (~lcr[7] & dl[7] & ~addr_i_c[0]) | 
   (~lcr[7] & addr_i_c[0]) | (~dl[15] & addr_i_c[0]) | (~lcr[7] & dl[15] & 
   addr_i_c[0]);
assign dat_o_8_1_0_am[7] = (~lcr[7] & addr_i_c[0] & dat_o_7_0_am_1[7]) | 
   (~lcr[7] & addr_i_c[0] & ~addr_i_c[2]) | (dat_o_7_0_am_1[7] & addr_i_c[2]);
// @9:442
  PFUMX \dat_o_8_1_0_cZ[4]  (
	.ALUT(dat_o_8_1_0_bm[4]),
	.BLUT(dat_o_8_1_0_am[4]),
	.C0(dat_o_sn_m7_0_a2),
	.Z(dat_o_8_1_0[4])
);
assign dat_o_8_1_0_bm[4] = (~lcr[7]) | (~lcr[7] & ~dl[4]) | (~dl[12] & 
   ~dl[4]) | (~lcr[7] & dl[12] & ~dl[4]) | (~lcr[7] & dl[4]) | (~lcr[7] & 
   ~addr_i_c[0]) | (~dl[4] & ~addr_i_c[0]) | (~lcr[7] & dl[4] & ~addr_i_c[0]) |