uart_regs.vhm

vlsi UART referene, use UART0_3

	  (DL(11) and LCR(7));
  DL15_1 <= not ADDR_I_C(1) and not ADDR_I_C(2) and not ADDR_I_C(3) and not ADDR_I_C(4);
  N_193 <= (not ADDR_I_C(2) and not ADDR_I_C(3) and not ADDR_I_C(4)) or 
	  (ADDR_I_C(0) and not ADDR_I_C(3) and not ADDR_I_C(4));
  N_194 <= ADDR_I_C(1) and not ADDR_I_C(3) and not ADDR_I_C(4);
  MCR8_2 <= not ADDR_I_C(0) and ADDR_I_C(2) and not ADDR_I_C(3) and not ADDR_I_C(4);
  N_198 <= (not IIR67_SN and not RLS_INT_PND) or 
	  (RDA_INT_PND and not RLS_INT_PND);
  N_208_1 <= (not IER(0) and not RLS_INT_PND) or 
	  (not RLS_INT_PND and UN5_RDA_INT_CRY_4);
  LCR6_2 <= ADDR_I_C(0) and not ADDR_I_C(3) and not ADDR_I_C(4) and WE_I_C;
  BLOCK_CNT_5(4) <= (not LCR(0) and not LCR(2) and not LCR(3)) or 
	  (LCR(0) and LCR(2) and not LCR(3)) or 
	  (LCR(0) and not LCR(2) and LCR(3)) or 
	  (not LCR(0) and LCR(2) and LCR(3));
  M2 <= not LCR(0) and not LCR(1) and LCR(2);
  UN1_THRE_SET_EN_4 <= not BLOCK_CNT(4) and not BLOCK_CNT(5) and not BLOCK_CNT(6) and not BLOCK_CNT(7);
  UN1_DL_8 <= not DL(8) and not DL(9) and not DL(10) and not DL(11);
  UN1_DL_9 <= not DL(12) and not DL(13) and not DL(14) and not DL(15);
  UN1_DL_10 <= not DL(0) and not DL(1) and not DL(2) and not DL(3);
  UN1_DLC_8 <= not DLC(8) and not DLC(9) and not DLC(10) and not DLC(11);
  UN1_DLC_9 <= not DLC(12) and not DLC(13) and not DLC(14) and not DLC(15);
  UN1_DLC_10 <= not DLC(0) and not DLC(1) and not DLC(2) and not DLC(3);
  UN1_DLC_11 <= not DLC(4) and not DLC(5) and not DLC(6) and not DLC(7);
  LSR_MASK_CONDITION_2 <= not ADDR_I_C(3) and not ADDR_I_C(4) and not LCR(7) and RE_I_C;
  UN4_THRE_INT_PND_1 <= IIR(1) and not IIR(2) and not LCR(7) and RE_I_C;
  BLOCK_CNT14_1 <= not LCR(7) and LSR5R and WE_I_C;
  MS_INT <= (IER(3) and not UN2_MS_INT_0) or 
	  (IER(3) and MSR(0)) or 
	  (IER(3) and MSR(1));
  MSR_4(3) <= (not DELAYED_MODEM_SIGNALS(3) and not MODEM_INPUTS_C(0) and not MSI_RESET) or 
	  (DELAYED_MODEM_SIGNALS(3) and MODEM_INPUTS_C(0) and not MSI_RESET) or 
	  (not MSI_RESET and MSR(3));
  MSR_4(2) <= (not DELAYED_MODEM_SIGNALS(2) and not MODEM_INPUTS_C(1) and not MSI_RESET) or 
	  (DELAYED_MODEM_SIGNALS(2) and MODEM_INPUTS_C(1) and not MSI_RESET) or 
	  (not MSI_RESET and MSR(2));
  MSR_4(1) <= (not DELAYED_MODEM_SIGNALS(1) and not MODEM_INPUTS_C(2) and not MSI_RESET) or 
	  (DELAYED_MODEM_SIGNALS(1) and MODEM_INPUTS_C(2) and not MSI_RESET) or 
	  (not MSI_RESET and MSR(1));
  MSR_4(0) <= (not DELAYED_MODEM_SIGNALS(0) and not MODEM_INPUTS_C(3) and not MSI_RESET) or 
	  (DELAYED_MODEM_SIGNALS(0) and MODEM_INPUTS_C(3) and not MSI_RESET) or 
	  (not MSI_RESET and MSR(0));
  UN17_THRE_INT_PND_I_M_2 <= (not LSR5R and not THRE_INT_PND) or 
	  (not IER(1)) or 
	  (THRE_INT_D and not THRE_INT_PND);
  IIR67 <= (not IER(0) and IIR67_SN and not RLS_INT_PND) or 
	  (IIR67_SN and not RLS_INT_PND and UN5_RDA_INT_CRY_4);
  DAT_O29 <= DAT_O_SN_M7_0_A2 and not ADDR_I_C(0) and not ADDR_I_C(3) and not ADDR_I_C(4);
  DAT_O31 <= not ADDR_I_C(0) and not ADDR_I_C(3) and not ADDR_I_C(4) and LCR6_1;
  SCRATCH7 <= ADDR_I_C(1) and ADDR_I_C(2) and LCR6_2;
  LSR_MASK_CONDITION <= ADDR_I_C(0) and not ADDR_I_C(1) and ADDR_I_C(2) and LSR_MASK_CONDITION_2;
  MSR_READ <= ADDR_I_C(1) and not LCR(7) and MCR8_2 and RE_I_C;
  MCR8 <= not ADDR_I_C(1) and MCR8_2 and WE_I_C;
  UN1_RDA_INT_1_0 <= N_208_1 and not IIR67_SN and not MS_INT_PND and not THRE_INT_PND;
  N_259 <= not BLOCK_CNT(0) and not BLOCK_CNT(1) and UN1_THRE_SET_EN_0 and UN1_THRE_SET_EN_4;
  UN1_DL_12 <= not DL(6) and not DL(7) and UN1_DL_0 and UN1_DL_10;
  UN1_DLC_12 <= UN1_DLC_10 and UN1_DLC_11;
  BLOCK_CNT_5(5) <= (LCR(0) and not LCR(1) and not LCR(3)) or 
	  (not LCR(0) and LCR(1) and not LCR(2) and not LCR(3)) or 
	  (not LCR(1) and LCR(2) and not LCR(3)) or 
	  (not LCR(1) and not LCR(2) and LCR(3)) or 
	  (not LCR(0) and not LCR(1) and LCR(3)) or 
	  (LCR(0) and LCR(1) and LCR(2) and LCR(3));
  BLOCK_CNT_5(6) <= (not LCR(1) and not LCR(3)) or 
	  (not LCR(0) and not LCR(2) and not LCR(3)) or 
	  (not LCR(1) and not LCR(2)) or 
	  (not LCR(0) and not LCR(1));
  N_192_I <= (RLS_INT_PND) or 
	  (not IIR67_SN and not RDA_INT and THRE_INT_PND);
  N_208_I <= (IER(0) and not UN5_RDA_INT_CRY_4) or 
	  (IIR67_SN) or 
	  (RLS_INT_PND);
  UN13_RDA_INT_PND_I_M_I <= (IER(0) and not RDA_INT_D and not UN5_RDA_INT_CRY_4) or 
	  (IER(0) and RDA_INT_PND);
  TX_RESET11 <= DAT_O31 and WE_I_C;
  FIFO_READ <= not ADDR_I_C(0) and DL15_1 and not LCR(7) and RE_I_C;
  IER_1_SQMUXA <= ADDR_I_C(0) and DL15_1 and not LCR(7) and WE_I_C;
  IER_0_SQMUXA <= ADDR_I_C(0) and DL15_1 and LCR(7) and WE_I_C;
  MSI_RESET13 <= not MSI_RESET and MSR_READ;
  MS_INT_RISE <= MS_INT and not MS_INT_D;
  N_214 <= UN1_DLC_8 and UN1_DLC_9 and UN1_DLC_10 and UN1_DLC_11;
  ENABLE10 <= (N_214 and not UN1_DL_12) or 
	  (N_214 and not UN1_DL_9) or 
	  (N_214 and not UN1_DL_8);
  DL_0_SQMUXA <= not ADDR_I_C(0) and DL15_1 and LCR(7) and WE_I_C;
  FIFO_WRITE <= not ADDR_I_C(0) and DL15_1 and not LCR(7) and WE_I_C;
  N_211 <= (not START_DLC and not UN1_DLC_12) or 
	  (not START_DLC and not UN1_DLC_9) or 
	  (not START_DLC and not UN1_DLC_8);
  BLOCK_CNT_LM(0) <= (BLOCK_CNT_S(0)) or 
	  (not ADDR_I_C(0) and BLOCK_CNT14_1 and DL15_1);
  BLOCK_CNT_LM(1) <= (BLOCK_CNT_S(1)) or 
	  (not ADDR_I_C(0) and BLOCK_CNT14_1 and DL15_1);
  BLOCK_CNT_LM(2) <= (BLOCK_CNT_S(2)) or 
	  (not ADDR_I_C(0) and BLOCK_CNT14_1 and DL15_1);
  UN13_TI_INT_PND_IV(0) <= not FIFO_READ and IER(0) and IIR67_SN;
  UN13_RLS_INT_PND_IV(0) <= (IER(2) and not LSR_MASK_CONDITION and RLS_INT_PND) or 
	  (IER(2) and LSR_MASK_D and RLS_INT_PND);
  BLOCK_CNT_LM(3) <= (BLOCK_CNT_S(3) and not DAT_O29) or 
	  (BLOCK_CNT14_1 and not M2 and DAT_O29) or 
	  (not M2 and BLOCK_CNT_S(3)) or 
	  (not BLOCK_CNT14_1 and BLOCK_CNT_S(3));
  BLOCK_CNT_LM(4) <= (BLOCK_CNT_S(4) and not DAT_O29) or 
	  (BLOCK_CNT14_1 and BLOCK_CNT_5(4) and DAT_O29) or 
	  (not BLOCK_CNT14_1 and BLOCK_CNT_S(4));
  BLOCK_CNT_LM(5) <= (BLOCK_CNT_S(5) and not DAT_O29) or 
	  (BLOCK_CNT14_1 and BLOCK_CNT_5(5) and DAT_O29) or 
	  (not BLOCK_CNT14_1 and BLOCK_CNT_S(5));
  BLOCK_CNT_LM(6) <= (BLOCK_CNT_S(6) and not DAT_O29) or 
	  (BLOCK_CNT14_1 and BLOCK_CNT_5(6) and DAT_O29) or 
	  (not BLOCK_CNT14_1 and BLOCK_CNT_S(6));
  BLOCK_CNT_LM(7) <= (BLOCK_CNT_S(7) and not DAT_O29) or 
	  (BLOCK_CNT14_1 and not BLOCK_CNT_5(6) and DAT_O29) or 
	  (not BLOCK_CNT_5(6) and BLOCK_CNT_S(7)) or 
	  (not BLOCK_CNT14_1 and BLOCK_CNT_S(7));
  N_201_I <= (BLOCK_CNT14_1 and DAT_O29) or 
	  (not N_259 and ENABLE);
  UN13_MS_INT_PND_IV(0) <= (IER(3) and MS_INT_PND and not MSR_READ) or 
	  (MS_INT_RISE and not MSR_READ);
  UN10_LSR6R_0(0) <= (N_259 and not FIFO_WRITE and not LSR6_D) or 
	  (not FIFO_WRITE and LSR6R);
  UN10_LSR5R_0(0) <= (N_259 and not FIFO_WRITE and not LSR6_D) or 
	  (not FIFO_WRITE and LSR5R);
  UN21_THRE_INT_PND_IV(0) <= (not FIFO_WRITE and not UN4_THRE_INT_PND_1 and not UN17_THRE_INT_PND_I_M_2) or 
	  (not DAT_O31 and not FIFO_WRITE and not UN17_THRE_INT_PND_I_M_2);
  UN30_INT_O_U_0_AM(0) <= (not FIFO_READ and not RLS_INT_PND) or 
	  (not LSR_MASK_CONDITION and RLS_INT_PND) or 
	  (LSR_MASK_D and RLS_INT_PND);
  UN30_INT_O_U_0_BM(0) <= (MS_INT_PND and not MSR_READ) or 
	  (RDA_INT_PND) or 
	  (THRE_INT_PND);
  \UN30_INT_O_U_0[0]_Z876\: PFUMX port map (
      ALUT => UN30_INT_O_U_0_BM(0),
      BLUT => UN30_INT_O_U_0_AM(0),
      C0 => N_198,
      Z => UN30_INT_O_U_0(0));
  DAT_O_C(0) <= (N_193 and not DAT_O_2_1_0(0)) or 
	  (N_194 and not DAT_O_2_1_0(0) and MSR(0)) or 
	  (not N_193 and N_194 and MSR(0));
  DAT_O_C(3) <= (N_193 and not DAT_O_8_1_0(3)) or 
	  (N_194 and not DAT_O_8_1_0(3) and MSR(3)) or 
	  (not N_193 and N_194 and MSR(3));
  DAT_O_C(5) <= (N_193 and not DAT_O_8_1_0(5)) or 
	  (N_194 and not DAT_O_8_1_0(5) and MSR(5)) or 
	  (not N_193 and N_194 and MSR(5));
  DAT_O_C(6) <= (N_193 and not DAT_O_8_1_0(6)) or 
	  (N_194 and not DAT_O_8_1_0(6) and MSR(6)) or 
	  (not N_193 and N_194 and MSR(6));
  DAT_O_C(4) <= (N_193 and not DAT_O_8_1_0(4)) or 
	  (N_194 and not DAT_O_8_1_0(4) and MSR(4)) or 
	  (not N_193 and N_194 and MSR(4));
  DAT_O_C(7) <= (N_193 and not DAT_O_8_1_0(7)) or 
	  (N_194 and not DAT_O_8_1_0(7) and MSR(7)) or 
	  (not N_193 and N_194 and MSR(7));
  DAT_O_7_0_AM_1(3) <= (ADDR_I_C(2) and not SCRATCH(3)) or 
	  (not ADDR_I_C(2) and not IIR(3)) or 
	  (not ADDR_I_C(1) and not IIR(3)) or 
	  (not ADDR_I_C(1) and ADDR_I_C(2));
  DAT_O_7_0_AM_1(0) <= (ADDR_I_C(2) and not SCRATCH(0)) or 
	  (not ADDR_I_C(2) and not IIR(0)) or 
	  (not ADDR_I_C(1) and not IIR(0)) or 
	  (not ADDR_I_C(1) and ADDR_I_C(2));
  DAT_O_7_0_AM_1(4) <= (not SCRATCH(4)) or 
	  (not ADDR_I_C(1));
  DAT_O_7_0_AM_1(7) <= (not SCRATCH(7)) or 
	  (not ADDR_I_C(1));
  M9_E <= DL(2) and LCR(7);
  M17_0 <= not ADDR_I_C(3) and not ADDR_I_C(4);
  DAT_O_C(2) <= (not N_9 and not DAT_O_SN_M7_0_A2 and M17_0) or 
	  (not N_15 and DAT_O_SN_M7_0_A2 and M17_0);
  M9_E_0 <= DL(1) and LCR(7);
  DAT_O_C(1) <= (DAT_O_SN_M7_0_A2 and not M14_0 and M17_0) or 
	  (not DAT_O_SN_M7_0_A2 and not M7_0 and M17_0);
  N_206_I <= (not LCR(6)) or 
	  (MCR(4));
  UN5_RDA_INT_CRY_2_0: CCU2 
  generic map(
    INIT0 => "0x5001",
    INIT1 => "0x5001",
    INJECT1_0 => "NO",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => FCR(0),
    B0 => GND,
    C0 => GND,
    D0 => GND,
    A1 => FCR(1),
    B1 => GND,
    C1 => GND,
    D1 => GND,
    CIN => UN5_RDA_INT_CRY_1,
    COUT0 => UN5_RDA_INT_CRY_2,
    COUT1 => UN5_RDA_INT_CRY_4,
    S0 => UN5_RDA_INT_CRY_2_0_S0,
    S1 => UN5_RDA_INT_CRY_2_0_S1);
  UN5_RDA_INT_CRY_0_0: CCU2 
  generic map(
    INIT0 => "0xe00e",
    INIT1 => "0x7007",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => FCR(0),
    B0 => FCR(1),
    C0 => GND,
    D0 => GND,
    A1 => FCR(0),
    B1 => FCR(1),
    C1 => GND,
    D1 => GND,
    CIN => GND,
    COUT0 => UN5_RDA_INT_CRY_0,
    COUT1 => UN5_RDA_INT_CRY_1,
    S0 => UN5_RDA_INT_CRY_0_0_S0,
    S1 => UN5_RDA_INT_CRY_0_0_S1);
  DLC_5_CRY_14_0: CCU2 
  generic map(
    INIT0 => "0x3327",
    INIT1 => "0x5027",
    INJECT1_0 => "YES",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => N_214,
    B0 => DL(14),
    C0 => DLC(14),
    D0 => START_DLC,
    A1 => N_211,
    B1 => DLC(15),
    C1 => DL(15),
    D1 => GND,
    CIN => DLC_5_CRY_13,
    COUT0 => DLC_5_CRY_14,
    COUT1 => DLC_5_CRY_14_0_COUT1,
    S0 => DLC_5(14),
    S1 => DLC_5(15));
  DLC_5_CRY_12_0: CCU2 
  generic map(
    INIT0 => "0x3327",
    INIT1 => "0x3327",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => N_214,
    B0 => DL(12),
    C0 => DLC(12),
    D0 => START_DLC,
    A1 => N_214,
    B1 => DL(13),
    C1 => DLC(13),
    D1 => START_DLC,
    CIN => DLC_5_CRY_11,
    COUT0 => DLC_5_CRY_12,
    COUT1 => DLC_5_CRY_13,
    S0 => DLC_5(12),
    S1 => DLC_5(13));
  DLC_5_CRY_10_0: CCU2 
  generic map(
    INIT0 => "0x3327",
    INIT1 => "0x3327",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => N_214,
    B0 => DL(10),
    C0 => DLC(10),
    D0 => START_DLC,
    A1 => N_214,
    B1 => DL(11),
    C1 => DLC(11),
    D1 => START_DLC,
    CIN => DLC_5_CRY_9,
    COUT0 => DLC_5_CRY_10,
    COUT1 => DLC_5_CRY_11,
    S0 => DLC_5(10),
    S1 => DLC_5(11));
  DLC_5_CRY_8_0: CCU2 
  generic map(
    INIT0 => "0x3327",
    INIT1 => "0x3327",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => N_214,
    B0 => DL(8),
    C0 => DLC(8),
    D0 => START_DLC,
    A1 => N_214,
    B1 => DL(9),
    C1 => DLC(9),
    D1 => START_DLC,
    CIN => DLC_5_CRY_7,
    COUT0 => DLC_5_CRY_8,
    COUT1 => DLC_5_CRY_9,
    S0 => DLC_5(8),
    S1 => DLC_5(9));
  DLC_5_CRY_6_0: CCU2 
  generic map(
    INIT0 => "0x3327",
    INIT1 => "0x3327",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => N_214,
    B0 => DL(6),
    C0 => DLC(6),
    D0 => START_DLC,
    A1 => N_214,
    B1 => DL(7),
    C1 => DLC(7),
    D1 => START_DLC,
    CIN => DLC_5_CRY_5,
    COUT0 => DLC_5_CRY_6,
    COUT1 => DLC_5_CRY_7,
    S0 => DLC_5(6),
    S1 => DLC_5(7));
  DLC_5_CRY_4_0: CCU2 
  generic map(
    INIT0 => "0x3327",
    INIT1 => "0x3327",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => N_214,
    B0 => DL(4),
    C0 => DLC(4),
    D0 => START_DLC,
    A1 => N_214,
    B1 => DL(5),
    C1 => DLC(5),
    D1 => START_DLC,
    CIN => DLC_5_CRY_3,
    COUT0 => DLC_5_CRY_4,
    COUT1 => DLC_5_CRY_5,
    S0 => DLC_5(4),
    S1 => DLC_5(5));
  DLC_5_CRY_2_0: CCU2 
  generic map(
    INIT0 => "0x3327",
    INIT1 => "0x3327",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => N_214,
    B0 => DL(2),
    C0 => DLC(2),
    D0 => START_DLC,
    A1 => N_214,
    B1 => DL(3),
    C1 => DLC(3),
    D1 => START_DLC,
    CIN => DLC_5_CRY_1,
    COUT0 => DLC_5_CRY_2,
    COUT1 => DLC_5_CRY_3,
    S0 => DLC_5(2),
    S1 => DLC_5(3));
  DLC_5_CRY_0_0: CCU2 
  generic map(
    INIT0 => "0x3327",
    INIT1 => "0x3327",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => N_214,
    B0 => DL(0),
    C0 => DLC(0),
    D0 => START_DLC,
    A1 => N_214,
    B1 => DL(1),
    C1 => DLC(1),
    D1 => START_DLC,
    CIN => GND,
    COUT0 => DLC_5_CRY_0,
    COUT1 => DLC_5_CRY_1,
    S0 => UN1_DLC_2_I(0),
    S1 => DLC_5(1));
  \BLOCK_CNT_CRY_0[6]\: CCU2 
  generic map(
    INIT0 => "0x5006",
    INIT1 => "0x5006",
    INJECT1_0 => "YES",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => BLOCK_CNT(6),
    B0 => VCC,
    C0 => GND,
    D0 => GND,
    A1 => BLOCK_CNT(7),
    B1 => VCC,
    C1 => GND,
    D1 => GND,
    CIN => BLOCK_CNT_CRY(5),
    COUT0 => BLOCK_CNT_CRY(6),
    COUT1 => BLOCK_CNT_CRY_0_COUT1(6),
    S0 => BLOCK_CNT_S(6),
    S1 => BLOCK_CNT_S(7));
  \BLOCK_CNT_CRY_0[4]\: CCU2 
  generic map(
    INIT0 => "0x5006",
    INIT1 => "0x5006",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => BLOCK_CNT(4),
    B0 => VCC,
    C0 => GND,
    D0 => GND,
    A1 => BLOCK_CNT(5),
    B1 => VCC,
    C1 => GND,
    D1 => GND,
    CIN => BLOCK_CNT_CRY(3),
    COUT0 => BLOCK_CNT_CRY(4),
    COUT1 => BLOCK_CNT_CRY(5),
    S0 => BLOCK_CNT_S(4),
    S1 => BLOCK_CNT_S(5));
  \BLOCK_CNT_CRY_0[2]\: CCU2 
  generic map(
    INIT0 => "0x5006",
    INIT1 => "0x5006",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => BLOCK_CNT(2),
    B0 => VCC,
    C0 => GND,
    D0 => GND,
    A1 => BLOCK_CNT(3),
    B1 => VCC,
    C1 => GND,
    D1 => GND,
    CIN => BLOCK_CNT_CRY(1),
    COUT0 => BLOCK_CNT_CRY(2),
    COUT1 => BLOCK_CNT_CRY(3),
    S0 => BLOCK_CNT_S(2),
    S1 => BLOCK_CNT_S(3));
  \BLOCK_CNT_CRY_0[0]\: CCU2 
  generic map(
    INIT0 => "0x5006",
    INIT1 => "0x5006",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => BLOCK_CNT(0),
    B0 => VCC,
    C0 => GND,
    D0 => GND,
    A1 => BLOCK_CNT(1),
    B1 => VCC,
    C1 => GND,
    D1 => GND,
    CIN => GND,
    COUT0 => BLOCK_CNT_CRY(0),
    COUT1 => BLOCK_CNT_CRY(1),
    S0 => BLOCK_CNT_S(0),
    S1 => BLOCK_CNT_S(1));
  NN_1 <= '0';
  NN_2 <= '1';
end beh;