uart_regs.vhm

vlsi UART referene, use UART0_3

      Q => MSR(6));
  \MSR[7]_REG\: FD1S3AX port map (
      D => UN7_DCD_C_0(0),
      CK => CLK_C,
      Q => MSR(7));
  MSI_RESET_REG: FD1S3AY port map (
      D => MSI_RESET13,
      CK => CLK_C,
      Q => MSI_RESET);
  MS_INT_PND_REG: FD1S3AX port map (
      D => UN13_MS_INT_PND_IV(0),
      CK => CLK_C,
      Q => MS_INT_PND);
  MS_INT_D_REG: FD1S3AX port map (
      D => MS_INT,
      CK => CLK_C,
      Q => MS_INT_D);
  \MCR[0]_REG\: FD1P3AX port map (
      D => DAT_I_C(0),
      SP => MCR8,
      CK => CLK_C,
      Q => MCR(0));
  \MCR[1]_REG\: FD1P3AX port map (
      D => DAT_I_C(1),
      SP => MCR8,
      CK => CLK_C,
      Q => MCR(1));
  \MCR[2]_REG\: FD1P3AX port map (
      D => DAT_I_C(2),
      SP => MCR8,
      CK => CLK_C,
      Q => MCR(2));
  \MCR[3]_REG\: FD1P3AX port map (
      D => DAT_I_C(3),
      SP => MCR8,
      CK => CLK_C,
      Q => MCR(3));
  \MCR[4]_REG\: FD1P3AX port map (
      D => DAT_I_C(4),
      SP => MCR8,
      CK => CLK_C,
      Q => MCR(4));
  LSR_MASK_D_REG: FD1S3AX port map (
      D => LSR_MASK_CONDITION,
      CK => CLK_C,
      Q => LSR_MASK_D);
  LSR6R_REG: FD1S3AY port map (
      D => UN10_LSR6R_0(0),
      CK => CLK_C,
      Q => LSR6R);
  LSR5R_REG: FD1S3AY port map (
      D => UN10_LSR5R_0(0),
      CK => CLK_C,
      Q => LSR5R);
  LSR5_D_REG: FD1S3AY port map (
      D => N_259,
      CK => CLK_C,
      Q => LSR6_D);
  \LCR[0]_REG\: FD1P3AY port map (
      D => DAT_I_C(0),
      SP => LCR6,
      CK => CLK_C,
      Q => LCR(0));
  \LCR[1]_REG\: FD1P3AY port map (
      D => DAT_I_C(1),
      SP => LCR6,
      CK => CLK_C,
      Q => LCR(1));
  \LCR[2]_REG\: FD1P3AX port map (
      D => DAT_I_C(2),
      SP => LCR6,
      CK => CLK_C,
      Q => LCR(2));
  \LCR[3]_REG\: FD1P3AX port map (
      D => DAT_I_C(3),
      SP => LCR6,
      CK => CLK_C,
      Q => LCR(3));
  \LCR[4]_REG\: FD1P3AX port map (
      D => DAT_I_C(4),
      SP => LCR6,
      CK => CLK_C,
      Q => LCR(4));
  \LCR[5]_REG\: FD1P3AX port map (
      D => DAT_I_C(5),
      SP => LCR6,
      CK => CLK_C,
      Q => LCR(5));
  \LCR[6]_REG\: FD1P3AX port map (
      D => DAT_I_C(6),
      SP => LCR6,
      CK => CLK_C,
      Q => LCR(6));
  \LCR[7]_REG\: FD1P3AX port map (
      D => DAT_I_C(7),
      SP => LCR6,
      CK => CLK_C,
      Q => LCR(7));
  \IIR[0]_REG\: FD1S3AY port map (
      D => UN1_RDA_INT_1_0,
      CK => CLK_C,
      Q => IIR(0));
  \IIR[1]_REG\: FD1S3AX port map (
      D => N_192_I,
      CK => CLK_C,
      Q => IIR(1));
  \IIR[2]_REG\: FD1S3AX port map (
      D => N_208_I,
      CK => CLK_C,
      Q => IIR(2));
  \IIR[3]_REG\: FD1S3AX port map (
      D => IIR67,
      CK => CLK_C,
      Q => IIR(3));
  \IER[0]_REG\: FD1P3AX port map (
      D => DAT_I_C(0),
      SP => IER_1_SQMUXA,
      CK => CLK_C,
      Q => IER(0));
  \IER[1]_REG\: FD1P3AX port map (
      D => DAT_I_C(1),
      SP => IER_1_SQMUXA,
      CK => CLK_C,
      Q => IER(1));
  \IER[2]_REG\: FD1P3AX port map (
      D => DAT_I_C(2),
      SP => IER_1_SQMUXA,
      CK => CLK_C,
      Q => IER(2));
  \IER[3]_REG\: FD1P3AX port map (
      D => DAT_I_C(3),
      SP => IER_1_SQMUXA,
      CK => CLK_C,
      Q => IER(3));
  \FCR[0]_REG\: FD1P3AY port map (
      D => DAT_I_C(6),
      SP => TX_RESET11,
      CK => CLK_C,
      Q => FCR(0));
  \FCR[1]_REG\: FD1P3AY port map (
      D => DAT_I_C(7),
      SP => TX_RESET11,
      CK => CLK_C,
      Q => FCR(1));
  ENABLE_REG: FD1S3AX port map (
      D => ENABLE10,
      CK => CLK_C,
      Q => ENABLE);
  \DL[0]_REG\: FD1P3AX port map (
      D => DAT_I_C(0),
      SP => DL_0_SQMUXA,
      CK => CLK_C,
      Q => DL(0));
  \DLC[0]_REG\: FD1S3AX port map (
      D => UN1_DLC_2_I(0),
      CK => CLK_C,
      Q => DLC(0));
  \DL[1]_REG\: FD1P3AX port map (
      D => DAT_I_C(1),
      SP => DL_0_SQMUXA,
      CK => CLK_C,
      Q => DL(1));
  \DLC[1]_REG\: FD1S3AX port map (
      D => DLC_5(1),
      CK => CLK_C,
      Q => DLC(1));
  \DL[2]_REG\: FD1P3AX port map (
      D => DAT_I_C(2),
      SP => DL_0_SQMUXA,
      CK => CLK_C,
      Q => DL(2));
  \DLC[2]_REG\: FD1S3AX port map (
      D => DLC_5(2),
      CK => CLK_C,
      Q => DLC(2));
  \DLC[3]_REG\: FD1S3AX port map (
      D => DLC_5(3),
      CK => CLK_C,
      Q => DLC(3));
  \DL[3]_REG\: FD1P3AX port map (
      D => DAT_I_C(3),
      SP => DL_0_SQMUXA,
      CK => CLK_C,
      Q => DL(3));
  \DLC[4]_REG\: FD1S3AX port map (
      D => DLC_5(4),
      CK => CLK_C,
      Q => DLC(4));
  \DL[4]_REG\: FD1P3AX port map (
      D => DAT_I_C(4),
      SP => DL_0_SQMUXA,
      CK => CLK_C,
      Q => DL(4));
  \DLC[5]_REG\: FD1S3AX port map (
      D => DLC_5(5),
      CK => CLK_C,
      Q => DLC(5));
  \DL[5]_REG\: FD1P3AX port map (
      D => DAT_I_C(5),
      SP => DL_0_SQMUXA,
      CK => CLK_C,
      Q => DL(5));
  \DL[6]_REG\: FD1P3AX port map (
      D => DAT_I_C(6),
      SP => DL_0_SQMUXA,
      CK => CLK_C,
      Q => DL(6));
  \DLC[6]_REG\: FD1S3AX port map (
      D => DLC_5(6),
      CK => CLK_C,
      Q => DLC(6));
  \DL[7]_REG\: FD1P3AX port map (
      D => DAT_I_C(7),
      SP => DL_0_SQMUXA,
      CK => CLK_C,
      Q => DL(7));
  \DLC[7]_REG\: FD1S3AX port map (
      D => DLC_5(7),
      CK => CLK_C,
      Q => DLC(7));
  \DLC[8]_REG\: FD1S3AX port map (
      D => DLC_5(8),
      CK => CLK_C,
      Q => DLC(8));
  \DL[8]_REG\: FD1P3AX port map (
      D => DAT_I_C(0),
      SP => IER_0_SQMUXA,
      CK => CLK_C,
      Q => DL(8));
  \DLC[9]_REG\: FD1S3AX port map (
      D => DLC_5(9),
      CK => CLK_C,
      Q => DLC(9));
  \DL[9]_REG\: FD1P3AX port map (
      D => DAT_I_C(1),
      SP => IER_0_SQMUXA,
      CK => CLK_C,
      Q => DL(9));
  \DLC[10]_REG\: FD1S3AX port map (
      D => DLC_5(10),
      CK => CLK_C,
      Q => DLC(10));
  \DL[10]_REG\: FD1P3AX port map (
      D => DAT_I_C(2),
      SP => IER_0_SQMUXA,
      CK => CLK_C,
      Q => DL(10));
  \DL[11]_REG\: FD1P3AX port map (
      D => DAT_I_C(3),
      SP => IER_0_SQMUXA,
      CK => CLK_C,
      Q => DL(11));
  \DLC[11]_REG\: FD1S3AX port map (
      D => DLC_5(11),
      CK => CLK_C,
      Q => DLC(11));
  \DL[12]_REG\: FD1P3AX port map (
      D => DAT_I_C(4),
      SP => IER_0_SQMUXA,
      CK => CLK_C,
      Q => DL(12));
  \DLC[12]_REG\: FD1S3AX port map (
      D => DLC_5(12),
      CK => CLK_C,
      Q => DLC(12));
  \DLC[13]_REG\: FD1S3AX port map (
      D => DLC_5(13),
      CK => CLK_C,
      Q => DLC(13));
  \DL[13]_REG\: FD1P3AX port map (
      D => DAT_I_C(5),
      SP => IER_0_SQMUXA,
      CK => CLK_C,
      Q => DL(13));
  \DLC[14]_REG\: FD1S3AX port map (
      D => DLC_5(14),
      CK => CLK_C,
      Q => DLC(14));
  \DL[14]_REG\: FD1P3AX port map (
      D => DAT_I_C(6),
      SP => IER_0_SQMUXA,
      CK => CLK_C,
      Q => DL(14));
  \DLC[15]_REG\: FD1S3AX port map (
      D => DLC_5(15),
      CK => CLK_C,
      Q => DLC(15));
  \DL[15]_REG\: FD1P3AX port map (
      D => DAT_I_C(7),
      SP => IER_0_SQMUXA,
      CK => CLK_C,
      Q => DL(15));
  \DELAYED_MODEM_SIGNALS[0]_REG\: FD1S3AX port map (
      D => MODEM_INPUTS_C_I(3),
      CK => CLK_C,
      Q => DELAYED_MODEM_SIGNALS(0));
  \DELAYED_MODEM_SIGNALS[1]_REG\: FD1S3AX port map (
      D => MODEM_INPUTS_C_I(2),
      CK => CLK_C,
      Q => DELAYED_MODEM_SIGNALS(1));
  \DELAYED_MODEM_SIGNALS[2]_REG\: FD1S3AX port map (
      D => MODEM_INPUTS_C_I(1),
      CK => CLK_C,
      Q => DELAYED_MODEM_SIGNALS(2));
  \DELAYED_MODEM_SIGNALS[3]_REG\: FD1S3AX port map (
      D => MODEM_INPUTS_C_I(0),
      CK => CLK_C,
      Q => DELAYED_MODEM_SIGNALS(3));
  \BLOCK_CNT[0]_REG\: FD1P3AX port map (
      D => BLOCK_CNT_LM(0),
      SP => N_201_I,
      CK => CLK_C,
      Q => BLOCK_CNT(0));
  \BLOCK_CNT[1]_REG\: FD1P3AX port map (
      D => BLOCK_CNT_LM(1),
      SP => N_201_I,
      CK => CLK_C,
      Q => BLOCK_CNT(1));
  \BLOCK_CNT[2]_REG\: FD1P3AX port map (
      D => BLOCK_CNT_LM(2),
      SP => N_201_I,
      CK => CLK_C,
      Q => BLOCK_CNT(2));
  \BLOCK_CNT[3]_REG\: FD1P3AX port map (
      D => BLOCK_CNT_LM(3),
      SP => N_201_I,
      CK => CLK_C,
      Q => BLOCK_CNT(3));
  \BLOCK_CNT[4]_REG\: FD1P3AX port map (
      D => BLOCK_CNT_LM(4),
      SP => N_201_I,
      CK => CLK_C,
      Q => BLOCK_CNT(4));
  \BLOCK_CNT[5]_REG\: FD1P3AX port map (
      D => BLOCK_CNT_LM(5),
      SP => N_201_I,
      CK => CLK_C,
      Q => BLOCK_CNT(5));
  \BLOCK_CNT[6]_REG\: FD1P3AX port map (
      D => BLOCK_CNT_LM(6),
      SP => N_201_I,
      CK => CLK_C,
      Q => BLOCK_CNT(6));
  \BLOCK_CNT[7]_REG\: FD1P3AX port map (
      D => BLOCK_CNT_LM(7),
      SP => N_201_I,
      CK => CLK_C,
      Q => BLOCK_CNT(7));
  GSR_INST: GSR port map (
      GSR => GSRN);
  II_GSRN: INV port map (
      A => RST_I_C,
      Z => GSRN);
  INT_O_PAD: OB port map (
      I => INT_O_C,
      O => int_o);
  DTR_PAD_O_PAD: OB port map (
      I => MCR(0),
      O => dtr_pad_o);
  RTS_PAD_O_PAD: OB port map (
      I => MCR(1),
      O => rts_pad_o);
  STX_PAD_O_PAD: OB port map (
      I => N_206_I,
      O => stx_pad_o);
  \MODEM_INPUTS_PAD[3]\: IB port map (
      I => modem_inputs(3),
      O => MODEM_INPUTS_C(3));
  \MODEM_INPUTS_PAD[2]\: IB port map (
      I => modem_inputs(2),
      O => MODEM_INPUTS_C(2));
  \MODEM_INPUTS_PAD[1]\: IB port map (
      I => modem_inputs(1),
      O => MODEM_INPUTS_C(1));
  \MODEM_INPUTS_PAD[0]\: IB port map (
      I => modem_inputs(0),
      O => MODEM_INPUTS_C(0));
  RE_I_PAD: IB port map (
      I => re_i,
      O => RE_I_C);
  WE_I_PAD: IB port map (
      I => we_i,
      O => WE_I_C);
  \DAT_O_PAD[7]\: OB port map (
      I => DAT_O_C(7),
      O => dat_o(7));
  \DAT_O_PAD[6]\: OB port map (
      I => DAT_O_C(6),
      O => dat_o(6));
  \DAT_O_PAD[5]\: OB port map (
      I => DAT_O_C(5),
      O => dat_o(5));
  \DAT_O_PAD[4]\: OB port map (
      I => DAT_O_C(4),
      O => dat_o(4));
  \DAT_O_PAD[3]\: OB port map (
      I => DAT_O_C(3),
      O => dat_o(3));
  \DAT_O_PAD[2]\: OB port map (
      I => DAT_O_C(2),
      O => dat_o(2));
  \DAT_O_PAD[1]\: OB port map (
      I => DAT_O_C(1),
      O => dat_o(1));
  \DAT_O_PAD[0]\: OB port map (
      I => DAT_O_C(0),
      O => dat_o(0));
  \DAT_I_PAD[7]\: IB port map (
      I => dat_i(7),
      O => DAT_I_C(7));
  \DAT_I_PAD[6]\: IB port map (
      I => dat_i(6),
      O => DAT_I_C(6));
  \DAT_I_PAD[5]\: IB port map (
      I => dat_i(5),
      O => DAT_I_C(5));
  \DAT_I_PAD[4]\: IB port map (
      I => dat_i(4),
      O => DAT_I_C(4));
  \DAT_I_PAD[3]\: IB port map (
      I => dat_i(3),
      O => DAT_I_C(3));
  \DAT_I_PAD[2]\: IB port map (
      I => dat_i(2),
      O => DAT_I_C(2));
  \DAT_I_PAD[1]\: IB port map (
      I => dat_i(1),
      O => DAT_I_C(1));
  \DAT_I_PAD[0]\: IB port map (
      I => dat_i(0),
      O => DAT_I_C(0));
  \ADDR_I_PAD[4]\: IB port map (
      I => addr_i(4),
      O => ADDR_I_C(4));
  \ADDR_I_PAD[3]\: IB port map (
      I => addr_i(3),
      O => ADDR_I_C(3));
  \ADDR_I_PAD[2]\: IB port map (
      I => addr_i(2),
      O => ADDR_I_C(2));
  \ADDR_I_PAD[1]\: IB port map (
      I => addr_i(1),
      O => ADDR_I_C(1));
  \ADDR_I_PAD[0]\: IB port map (
      I => addr_i(0),
      O => ADDR_I_C(0));
  RST_I_PAD: IB port map (
      I => rst_i,
      O => RST_I_C);
  CLK_PAD: IB port map (
      I => clk,
      O => CLK_C);
  LCR6_1 <= ADDR_I_C(1) and not ADDR_I_C(2);
  DAT_O_SN_M7_0_A2 <= not ADDR_I_C(1) and not ADDR_I_C(2);
  RDA_INT <= IER(0) and not UN5_RDA_INT_CRY_4;
  THRE_INT <= IER(1) and LSR5R;
  UN2_MS_INT_0 <= not MSR(2) and not MSR(3);
  UN1_THRE_SET_EN_0 <= not BLOCK_CNT(2) and not BLOCK_CNT(3);
  UN1_DL_0 <= not DL(4) and not DL(5);
  N_57 <= (IER(0) and not LCR(7)) or 
	  (DL(8) and LCR(7));
  N_35 <= (not ADDR_I_C(1) and LSR5R) or 
	  (ADDR_I_C(1) and SCRATCH(5));
  UN7_DCD_C_0(3) <= (MCR(1) and MCR(4)) or 
	  (not MCR(4) and MODEM_INPUTS_C(3));
  UN7_DCD_C_0(2) <= (MCR(0) and MCR(4)) or 
	  (not MCR(4) and MODEM_INPUTS_C(2));
  UN7_DCD_C_0(1) <= (MCR(2) and MCR(4)) or 
	  (not MCR(4) and MODEM_INPUTS_C(1));
  UN7_DCD_C_0(0) <= (MCR(3) and MCR(4)) or 
	  (not MCR(4) and MODEM_INPUTS_C(0));
  N_36 <= (not ADDR_I_C(1) and LSR6R) or 
	  (ADDR_I_C(1) and SCRATCH(6));
  DAT_O_3_0(3) <= (IER(3) and not LCR(7)) or