📄 uart_regs.vhm
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--
-- Written by Synplicity
-- Product Version "Version 8.8L2"
-- Program "Synplify", Mapper "8.8.0, Build 018R"
-- Sat Mar 07 01:35:10 2009
--
--
-- Written by Synplify version 8.8.0, Build 018R
-- Sat Mar 07 01:35:10 2009
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library xp;
use xp.components.all;
entity uart_regs is
port(
clk : in std_logic;
rst_i : in std_logic;
addr_i : in std_logic_vector(4 downto 0);
dat_i : in std_logic_vector(7 downto 0);
dat_o : out std_logic_vector(7 downto 0);
we_i : in std_logic;
re_i : in std_logic;
modem_inputs : in std_logic_vector(3 downto 0);
stx_pad_o : out std_logic;
srx_pad_i : in std_logic;
rts_pad_o : out std_logic;
dtr_pad_o : out std_logic;
int_o : out std_logic);
end uart_regs;
architecture beh of uart_regs is
signal LCR : std_logic_vector(7 downto 0);
signal FCR : std_logic_vector(1 downto 0);
signal IIR : std_logic_vector(3 downto 0);
signal MCR : std_logic_vector(4 downto 0);
signal IER : std_logic_vector(3 downto 0);
signal DELAYED_MODEM_SIGNALS : std_logic_vector(3 downto 0);
signal UN7_DCD_C_0 : std_logic_vector(3 downto 0);
signal MSR : std_logic_vector(7 downto 0);
signal BLOCK_CNT : std_logic_vector(7 downto 0);
signal DLC : std_logic_vector(15 downto 0);
signal SCRATCH : std_logic_vector(7 downto 0);
signal DL : std_logic_vector(15 downto 0);
signal MSR_4 : std_logic_vector(3 downto 0);
signal UN10_LSR5R_0 : std_logic_vector(0 to 0);
signal UN10_LSR6R_0 : std_logic_vector(0 to 0);
signal DLC_5 : std_logic_vector(15 downto 1);
signal BLOCK_CNT_5 : std_logic_vector(6 downto 4);
signal UN30_INT_O_U_0 : std_logic_vector(0 to 0);
signal DAT_O_3_0 : std_logic_vector(3 to 3);
signal UN21_THRE_INT_PND_IV : std_logic_vector(0 to 0);
signal UN13_TI_INT_PND_IV : std_logic_vector(0 to 0);
signal UN13_MS_INT_PND_IV : std_logic_vector(0 to 0);
signal UN13_RLS_INT_PND_IV : std_logic_vector(0 to 0);
signal UN1_DLC_2_I : std_logic_vector(0 to 0);
signal BLOCK_CNT_CRY : std_logic_vector(6 downto 0);
signal BLOCK_CNT_S : std_logic_vector(7 downto 0);
signal BLOCK_CNT_LM : std_logic_vector(7 downto 0);
signal BLOCK_CNT_CRY_0_COUT1 : std_logic_vector(6 to 6);
signal UN30_INT_O_U_0_AM : std_logic_vector(0 to 0);
signal UN30_INT_O_U_0_BM : std_logic_vector(0 to 0);
signal DAT_O_2_1_0 : std_logic_vector(0 to 0);
signal DAT_O_8_1_0 : std_logic_vector(7 downto 3);
signal DAT_O_7_0_AM_1 : std_logic_vector(7 downto 0);
signal ADDR_I_C : std_logic_vector(4 downto 0);
signal DAT_I_C : std_logic_vector(7 downto 0);
signal DAT_O_C : std_logic_vector(7 downto 0);
signal MODEM_INPUTS_C : std_logic_vector(3 downto 0);
signal BLOCK_CNT_QN : std_logic_vector(7 downto 0);
signal DELAYED_MODEM_SIGNALS_QN : std_logic_vector(3 downto 0);
signal DL_QN : std_logic_vector(15 downto 0);
signal DLC_QN : std_logic_vector(15 downto 0);
signal FCR_QN : std_logic_vector(1 downto 0);
signal IER_QN : std_logic_vector(3 downto 0);
signal IIR_QN : std_logic_vector(3 downto 0);
signal LCR_QN : std_logic_vector(7 downto 0);
signal MCR_QN : std_logic_vector(4 downto 0);
signal MSR_QN : std_logic_vector(7 downto 0);
signal SCRATCH_QN : std_logic_vector(7 downto 0);
signal MODEM_INPUTS_C_I : std_logic_vector(3 downto 0);
signal DAT_O_8_1_0_AM : std_logic_vector(7 downto 3);
signal DAT_O_8_1_0_BM : std_logic_vector(7 downto 3);
signal DAT_O_2_1_0_AM : std_logic_vector(0 to 0);
signal DAT_O_2_1_0_BM : std_logic_vector(0 to 0);
signal ENABLE : std_logic ;
signal LSR_MASK_D : std_logic ;
signal MSI_RESET : std_logic ;
signal LSR6_D : std_logic ;
signal RDA_INT_D : std_logic ;
signal THRE_INT_D : std_logic ;
signal MS_INT_D : std_logic ;
signal RLS_INT_PND : std_logic ;
signal RDA_INT_PND : std_logic ;
signal THRE_INT_PND : std_logic ;
signal MS_INT_PND : std_logic ;
signal IIR67_SN : std_logic ;
signal THRE_INT : std_logic ;
signal LSR5R : std_logic ;
signal MCR8 : std_logic ;
signal LSR_MASK_CONDITION : std_logic ;
signal FIFO_WRITE : std_logic ;
signal LCR6 : std_logic ;
signal TX_RESET11 : std_logic ;
signal SCRATCH7 : std_logic ;
signal DL_0_SQMUXA : std_logic ;
signal MS_INT : std_logic ;
signal START_DLC : std_logic ;
signal MSI_RESET13 : std_logic ;
signal IER_0_SQMUXA : std_logic ;
signal IER_1_SQMUXA : std_logic ;
signal ENABLE10 : std_logic ;
signal RDA_INT : std_logic ;
signal LSR6R : std_logic ;
signal IIR67 : std_logic ;
signal UN1_RDA_INT_1_0 : std_logic ;
signal M2 : std_logic ;
signal DAT_O_SN_M7_0_A2 : std_logic ;
signal UN5_RDA_INT_CRY_0 : std_logic ;
signal UN5_RDA_INT_CRY_1 : std_logic ;
signal UN5_RDA_INT_CRY_2 : std_logic ;
signal UN5_RDA_INT_CRY_4 : std_logic ;
signal N_214 : std_logic ;
signal DAT_O31 : std_logic ;
signal FIFO_READ : std_logic ;
signal LCR6_1 : std_logic ;
signal LCR6_2 : std_logic ;
signal DAT_O29 : std_logic ;
signal MSR_READ : std_logic ;
signal N_36 : std_logic ;
signal N_193 : std_logic ;
signal N_194 : std_logic ;
signal N_35 : std_logic ;
signal DL15_1 : std_logic ;
signal N_259 : std_logic ;
signal N_278 : std_logic ;
signal N_280 : std_logic ;
signal N_281 : std_logic ;
signal N_206_I : std_logic ;
signal N_282 : std_logic ;
signal N_283 : std_logic ;
signal N_284 : std_logic ;
signal N_285 : std_logic ;
signal N_286 : std_logic ;
signal N_287 : std_logic ;
signal MCR8_2 : std_logic ;
signal N_57 : std_logic ;
signal MS_INT_RISE : std_logic ;
signal N_198 : std_logic ;
signal UN17_THRE_INT_PND_I_M_2 : std_logic ;
signal N_208_1 : std_logic ;
signal DLC_5_CRY_0 : std_logic ;
signal DLC_5_CRY_1 : std_logic ;
signal DLC_5_CRY_2 : std_logic ;
signal DLC_5_CRY_3 : std_logic ;
signal DLC_5_CRY_4 : std_logic ;
signal DLC_5_CRY_5 : std_logic ;
signal DLC_5_CRY_6 : std_logic ;
signal DLC_5_CRY_7 : std_logic ;
signal DLC_5_CRY_8 : std_logic ;
signal DLC_5_CRY_9 : std_logic ;
signal DLC_5_CRY_10 : std_logic ;
signal DLC_5_CRY_11 : std_logic ;
signal DLC_5_CRY_12 : std_logic ;
signal DLC_5_CRY_13 : std_logic ;
signal DLC_5_CRY_14 : std_logic ;
signal N_211 : std_logic ;
signal UN13_RDA_INT_PND_I_M_I : std_logic ;
signal N_208_I : std_logic ;
signal N_192_I : std_logic ;
signal N_201_I : std_logic ;
signal N_581 : std_logic ;
signal N_582 : std_logic ;
signal N_583 : std_logic ;
signal N_584 : std_logic ;
signal UN2_MS_INT_0 : std_logic ;
signal UN1_THRE_SET_EN_0 : std_logic ;
signal UN1_THRE_SET_EN_4 : std_logic ;
signal UN1_DL_0 : std_logic ;
signal UN1_DL_8 : std_logic ;
signal UN1_DL_9 : std_logic ;
signal UN1_DL_10 : std_logic ;
signal UN1_DL_12 : std_logic ;
signal UN1_DLC_8 : std_logic ;
signal UN1_DLC_9 : std_logic ;
signal UN1_DLC_10 : std_logic ;
signal UN1_DLC_11 : std_logic ;
signal UN1_DLC_12 : std_logic ;
signal LSR_MASK_CONDITION_2 : std_logic ;
signal UN4_THRE_INT_PND_1 : std_logic ;
signal BLOCK_CNT14_1 : std_logic ;
signal UN5_RDA_INT_CRY_0_0_S0 : std_logic ;
signal DLC_5_CRY_14_0_COUT1 : std_logic ;
signal UN5_RDA_INT_CRY_0_0_S1 : std_logic ;
signal UN5_RDA_INT_CRY_2_0_S0 : std_logic ;
signal UN5_RDA_INT_CRY_2_0_S1 : std_logic ;
signal N_9 : std_logic ;
signal M9_E : std_logic ;
signal N_15 : std_logic ;
signal M17_0 : std_logic ;
signal M7_0 : std_logic ;
signal M9_E_0 : std_logic ;
signal M14_0 : std_logic ;
signal GND : std_logic ;
signal VCC : std_logic ;
signal CLK_C : std_logic ;
signal RST_I_C : std_logic ;
signal WE_I_C : std_logic ;
signal RE_I_C : std_logic ;
signal INT_O_C : std_logic ;
signal GSRN : std_logic ;
signal ENABLE_QN : std_logic ;
signal LSR5_D_QN : std_logic ;
signal LSR5R_QN : std_logic ;
signal LSR6R_QN : std_logic ;
signal LSR_MASK_D_QN : std_logic ;
signal MS_INT_D_QN : std_logic ;
signal MS_INT_PND_QN : std_logic ;
signal MSI_RESET_QN : std_logic ;
signal RDA_INT_D_QN : std_logic ;
signal RDA_INT_PND_QN : std_logic ;
signal RLS_INT_PND_QN : std_logic ;
signal START_DLC_QN : std_logic ;
signal THRE_INT_D_QN : std_logic ;
signal THRE_INT_PND_QN : std_logic ;
signal TI_INT_PND_QN : std_logic ;
signal M7_AM : std_logic ;
signal M7_BM : std_logic ;
signal M7_0_AM : std_logic ;
signal M7_0_BM : std_logic ;
signal M14_AM : std_logic ;
signal M14_BM : std_logic ;
signal M14_0_AM : std_logic ;
signal M14_0_BM : std_logic ;
signal NN_1 : std_logic ;
signal NN_2 : std_logic ;
begin
PUR_INST: PUR port map (
PUR => VCC);
VCC_0: VHI port map (
Z => VCC);
GND_0: VLO port map (
Z => GND);
\MODEM_INPUTS_C_I[0]_Z523\: INV port map (
A => MODEM_INPUTS_C(0),
Z => MODEM_INPUTS_C_I(0));
\MODEM_INPUTS_C_I[1]_Z524\: INV port map (
A => MODEM_INPUTS_C(1),
Z => MODEM_INPUTS_C_I(1));
\MODEM_INPUTS_C_I[2]_Z525\: INV port map (
A => MODEM_INPUTS_C(2),
Z => MODEM_INPUTS_C_I(2));
\MODEM_INPUTS_C_I[3]_Z526\: INV port map (
A => MODEM_INPUTS_C(3),
Z => MODEM_INPUTS_C_I(3));
LCR6 <= LCR6_2 and not ADDR_I_C(2) and ADDR_I_C(1);
M14_0_Z528: PFUMX port map (
ALUT => M14_0_BM,
BLUT => M14_0_AM,
C0 => ADDR_I_C(0),
Z => M14_0);
M14_0_BM <= (LCR(7) and not DL(9)) or
(not LCR(7) and not IER(1));
M14_0_AM <= (not ADDR_I_C(2) and not M9_E_0) or
(not MSR(1) and not M9_E_0) or
(ADDR_I_C(2) and not ADDR_I_C(1)) or
(not MSR(1) and ADDR_I_C(2));
M14: PFUMX port map (
ALUT => M14_BM,
BLUT => M14_AM,
C0 => ADDR_I_C(0),
Z => N_15);
M14_BM <= (LCR(7) and not DL(10)) or
(not LCR(7) and not IER(2));
M14_AM <= (not ADDR_I_C(2) and not M9_E) or
(not MSR(2) and not M9_E) or
(ADDR_I_C(2) and not ADDR_I_C(1)) or
(not MSR(2) and ADDR_I_C(2));
\DAT_O_8_1_0[6]_Z534\: PFUMX port map (
ALUT => DAT_O_8_1_0_BM(6),
BLUT => DAT_O_8_1_0_AM(6),
C0 => DAT_O_SN_M7_0_A2,
Z => DAT_O_8_1_0(6));
DAT_O_8_1_0_BM(6) <= (not DL(6) and not ADDR_I_C(0)) or
(not LCR(7)) or
(not DL(14) and ADDR_I_C(0));
DAT_O_8_1_0_AM(6) <= (ADDR_I_C(2) and not N_36) or
(ADDR_I_C(0) and not LCR(6) and not ADDR_I_C(2));
\DAT_O_8_1_0[5]_Z537\: PFUMX port map (
ALUT => DAT_O_8_1_0_BM(5),
BLUT => DAT_O_8_1_0_AM(5),
C0 => DAT_O_SN_M7_0_A2,
Z => DAT_O_8_1_0(5));
DAT_O_8_1_0_BM(5) <= (not DL(5) and not ADDR_I_C(0)) or
(not LCR(7)) or
(not DL(13) and ADDR_I_C(0));
DAT_O_8_1_0_AM(5) <= (ADDR_I_C(2) and not N_35) or
(not LCR(5) and not ADDR_I_C(2)) or
(not ADDR_I_C(0) and not ADDR_I_C(2));
\DAT_O_8_1_0[3]_Z540\: PFUMX port map (
ALUT => DAT_O_8_1_0_BM(3),
BLUT => DAT_O_8_1_0_AM(3),
C0 => DAT_O_SN_M7_0_A2,
Z => DAT_O_8_1_0(3));
DAT_O_8_1_0_BM(3) <= (ADDR_I_C(0) and not DAT_O_3_0(3)) or
(not DL(3) and not ADDR_I_C(0)) or
(not LCR(7) and not ADDR_I_C(0));
DAT_O_8_1_0_AM(3) <= (ADDR_I_C(0) and not LCR(3) and not ADDR_I_C(2)) or
(not LCR(3) and DAT_O_7_0_AM_1(3)) or
(not ADDR_I_C(0) and DAT_O_7_0_AM_1(3)) or
(DAT_O_7_0_AM_1(3) and ADDR_I_C(2));
\DAT_O_2_1_0[0]_Z543\: PFUMX port map (
ALUT => DAT_O_2_1_0_BM(0),
BLUT => DAT_O_2_1_0_AM(0),
C0 => DAT_O_SN_M7_0_A2,
Z => DAT_O_2_1_0(0));
DAT_O_2_1_0_BM(0) <= (ADDR_I_C(0) and not N_57) or
(not DL(0) and not ADDR_I_C(0)) or
(not LCR(7) and not ADDR_I_C(0));
DAT_O_2_1_0_AM(0) <= (ADDR_I_C(0) and not LCR(0) and not ADDR_I_C(2)) or
(not LCR(0) and DAT_O_7_0_AM_1(0)) or
(not ADDR_I_C(0) and DAT_O_7_0_AM_1(0)) or
(DAT_O_7_0_AM_1(0) and ADDR_I_C(2));
M7_0_Z546: PFUMX port map (
ALUT => M7_0_BM,
BLUT => M7_0_AM,
C0 => ADDR_I_C(0),
Z => M7_0);
M7_0_BM <= (ADDR_I_C(2) and not ADDR_I_C(1)) or
(not LCR(1) and not ADDR_I_C(2)) or
(not SCRATCH(1) and ADDR_I_C(2));
M7_0_AM <= (not ADDR_I_C(2) and not IIR(1)) or
(ADDR_I_C(2) and not MSR(1)) or
(ADDR_I_C(2) and not ADDR_I_C(1));
M7: PFUMX port map (
ALUT => M7_BM,
BLUT => M7_AM,
C0 => ADDR_I_C(0),
Z => N_9);
M7_BM <= (not ADDR_I_C(2) and not LCR(2)) or
(ADDR_I_C(2) and not SCRATCH(2)) or
(ADDR_I_C(2) and not ADDR_I_C(1));
M7_AM <= (ADDR_I_C(2) and not ADDR_I_C(1)) or
(not IIR(2) and not ADDR_I_C(2)) or
(not MSR(2) and ADDR_I_C(2));
\DAT_O_8_1_0[7]_Z552\: PFUMX port map (
ALUT => DAT_O_8_1_0_BM(7),
BLUT => DAT_O_8_1_0_AM(7),
C0 => DAT_O_SN_M7_0_A2,
Z => DAT_O_8_1_0(7));
DAT_O_8_1_0_BM(7) <= (not DL(7) and not ADDR_I_C(0)) or
(not LCR(7)) or
(not DL(15) and ADDR_I_C(0));
DAT_O_8_1_0_AM(7) <= (not LCR(7) and ADDR_I_C(0) and not ADDR_I_C(2)) or
(DAT_O_7_0_AM_1(7) and ADDR_I_C(2));
\DAT_O_8_1_0[4]_Z555\: PFUMX port map (
ALUT => DAT_O_8_1_0_BM(4),
BLUT => DAT_O_8_1_0_AM(4),
C0 => DAT_O_SN_M7_0_A2,
Z => DAT_O_8_1_0(4));
DAT_O_8_1_0_BM(4) <= (not DL(4) and not ADDR_I_C(0)) or
(not LCR(7)) or
(not DL(12) and ADDR_I_C(0));
DAT_O_8_1_0_AM(4) <= (not LCR(4) and not ADDR_I_C(2)) or
(not ADDR_I_C(0) and not ADDR_I_C(2)) or
(DAT_O_7_0_AM_1(4) and ADDR_I_C(2));
INT_O_0IO_REG: OFS1P3DX port map (
D => UN30_INT_O_U_0(0),
SP => VCC,
SCLK => CLK_C,
CD => GND,
Q => INT_O_C);
TI_INT_PND_REG: FD1S3AX port map (
D => UN13_TI_INT_PND_IV(0),
CK => CLK_C,
Q => IIR67_SN);
THRE_INT_PND_REG: FD1S3AX port map (
D => UN21_THRE_INT_PND_IV(0),
CK => CLK_C,
Q => THRE_INT_PND);
THRE_INT_D_REG: FD1S3AX port map (
D => THRE_INT,
CK => CLK_C,
Q => THRE_INT_D);
START_DLC_REG: FD1S3AX port map (
D => DL_0_SQMUXA,
CK => CLK_C,
Q => START_DLC);
\SCRATCH[0]_REG\: FD1P3AX port map (
D => DAT_I_C(0),
SP => SCRATCH7,
CK => CLK_C,
Q => SCRATCH(0));
\SCRATCH[1]_REG\: FD1P3AX port map (
D => DAT_I_C(1),
SP => SCRATCH7,
CK => CLK_C,
Q => SCRATCH(1));
\SCRATCH[2]_REG\: FD1P3AX port map (
D => DAT_I_C(2),
SP => SCRATCH7,
CK => CLK_C,
Q => SCRATCH(2));
\SCRATCH[3]_REG\: FD1P3AX port map (
D => DAT_I_C(3),
SP => SCRATCH7,
CK => CLK_C,
Q => SCRATCH(3));
\SCRATCH[4]_REG\: FD1P3AX port map (
D => DAT_I_C(4),
SP => SCRATCH7,
CK => CLK_C,
Q => SCRATCH(4));
\SCRATCH[5]_REG\: FD1P3AX port map (
D => DAT_I_C(5),
SP => SCRATCH7,
CK => CLK_C,
Q => SCRATCH(5));
\SCRATCH[6]_REG\: FD1P3AX port map (
D => DAT_I_C(6),
SP => SCRATCH7,
CK => CLK_C,
Q => SCRATCH(6));
\SCRATCH[7]_REG\: FD1P3AX port map (
D => DAT_I_C(7),
SP => SCRATCH7,
CK => CLK_C,
Q => SCRATCH(7));
RLS_INT_PND_REG: FD1S3AX port map (
D => UN13_RLS_INT_PND_IV(0),
CK => CLK_C,
Q => RLS_INT_PND);
RDA_INT_PND_REG: FD1S3AX port map (
D => UN13_RDA_INT_PND_I_M_I,
CK => CLK_C,
Q => RDA_INT_PND);
RDA_INT_D_REG: FD1S3AX port map (
D => RDA_INT,
CK => CLK_C,
Q => RDA_INT_D);
\MSR[0]_REG\: FD1S3AX port map (
D => MSR_4(0),
CK => CLK_C,
Q => MSR(0));
\MSR[1]_REG\: FD1S3AX port map (
D => MSR_4(1),
CK => CLK_C,
Q => MSR(1));
\MSR[2]_REG\: FD1S3AX port map (
D => MSR_4(2),
CK => CLK_C,
Q => MSR(2));
\MSR[3]_REG\: FD1S3AX port map (
D => MSR_4(3),
CK => CLK_C,
Q => MSR(3));
\MSR[4]_REG\: FD1S3AX port map (
D => UN7_DCD_C_0(3),
CK => CLK_C,
Q => MSR(4));
\MSR[5]_REG\: FD1S3AX port map (
D => UN7_DCD_C_0(2),
CK => CLK_C,
Q => MSR(5));
\MSR[6]_REG\: FD1S3AX port map (
D => UN7_DCD_C_0(1),
CK => CLK_C,
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