run_options.txt

vlsi UART referene, use UART0_3

#-- Synplicity, Inc.
#-- Version Synplify for Lattice 8.8L2
#-- Project file F:\new_uart\uart0_2\uart0_3\run_options.txt
#-- Written on Sat Mar 07 01:34:55 2009


#add_file options
add_file -verilog "C:/ispTOOLS7_0/ispcpld/../cae_library/synthesis/verilog/XP.v"
add_file -verilog "uart_3.h"
add_file -verilog "uart_receiver.v"
add_file -verilog "uart_sync_flops.v"
add_file -verilog "uart_transmitter.v"
add_file -verilog "uart_regs.v"


#implementation: "uart0_3"
impl -add uart0_3 -type fpga

#device options
set_option -technology LATTICE-XP
set_option -part LFXP10C
set_option -package F388C
set_option -speed_grade -5
set_option -part_companion ""

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -top_module "uart_regs"

#map options
set_option -frequency 200.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 0
set_option -force_gsr auto
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 1
set_option -write_vhdl 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 0

#set result format/file last
project -result_file "./uart_regs.edi"

#
#implementation attributes

set_option -vlog_std v2001
set_option -num_critical_paths 3
set_option -num_startend_points 0
set_option -auto_constrain_io true
impl -active "uart0_3"