uart_regs.cmd

vlsi UART referene, use UART0_3

STYFILENAME: uart_3.sty
PROJECT: uart_regs
WORKING_PATH: "f:/new_uart/uart0_2/uart0_3"
MODULE: uart_regs
VERILOG_FILE_LIST: "C:/ispTOOLS7_0/ispcpld/../cae_library/synthesis/verilog/XP.v" uart_3.h uart_receiver.v uart_sync_flops.v uart_transmitter.v uart_regs.v
OUTPUT_FILE_NAME: uart_regs
SUFFIX_NAME: edi
WRITE_PRF: false
Vlog_std_v2001: true
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:  3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:  0