traplog.tlg

vlsi UART referene, use UART0_3

@N: CD630 :".\gentmp0a02216":4:7:4:9|Synthesizing work.top.gen 
@N: CD630 :"syng0a02216":71:7:71:12|Synthesizing work.cmp_eq.cell_level 
@W: CD639 :"syng0a02216":94:11:94:18|Bit <2> of signal data_tmp is undriven 
@W: CD639 :"syng0a02216":94:11:94:18|Bit <3> of signal data_tmp is undriven 
@W: CD639 :"syng0a02216":94:11:94:18|Bit <4> of signal data_tmp is undriven 
@N: CD630 :"syng0a02216":39:7:39:23|Synthesizing work.eq_element_onebit.eqn 
@W: CD280 :"syng0a02216":48:11:48:17|Unbound component MUXCY_L mapped to black box
@N: CD630 :"syng0a02216":48:11:48:17|Synthesizing work.muxcy_l.syn_black_box 
Post processing for work.muxcy_l.syn_black_box
Post processing for work.eq_element_onebit.eqn
@N: CD630 :"syng0a02216":8:7:8:16|Synthesizing work.eq_element.eqn 
Post processing for work.eq_element.eqn
Post processing for work.cmp_eq.cell_level
Post processing for work.top.gen