uart_regs.plg

来自「vlsi UART referene, use UART0_3」· PLG 代码 · 共 13 行

@P:  Worst Slack : -3.397
@P:  uart_regs|clk - Estimated Frequency : 133.2 MHz
@P:  uart_regs|clk - Requested Frequency : 200.0 MHz
@P:  uart_regs|clk - Estimated Period : 7.507
@P:  uart_regs|clk - Requested Period : 5.000
@P:  uart_regs|clk - Slack : -2.507
@P:  System - Estimated Frequency : 119.1 MHz
@P:  System - Requested Frequency : 200.0 MHz
@P:  System - Estimated Period : 8.397
@P:  System - Requested Period : 5.000
@P:  System - Slack : -3.397
@P:  CPU Time : 0h:00m:06s