u_rec.v

Verilog实现mini-uart

//============================================================================
//
//        Title     : UART RECIEVER DESIGN
//        Author    : JP LIU
//
//=============================================================================
//
//        File Name      : u_rec.v
//        Module Name    : u_rec
//
//=============================================================================
//
// This is the receiver portion of the UART.
//
//=============================================================================

`include "uart_inc.h"

module u_rec
(	
  // system connections
  sys_rst_b,
  sys_clk,

  // uart
  uart_dataH,

  // output port
  rec_dataH,
  rec_readyH
);


////////////////////////////////////////////// 
//
// INPUT AND OUTPUT DECLARATION             //
//
//////////////////////////////////////////////

input		sys_rst_b;	// async reset
input		sys_clk;	// main clock must be 16 x Baud Rate
input		uart_dataH;	// goes to the UART pin

output	[7:0]	rec_dataH;	// parallel received data
output		rec_readyH;	// when high, new data is ok to be read


/////////////////////////////////////////////
//
// WIRE AND REG DECLARATION                //
//
/////////////////////////////////////////////

reg	[2:0]	next_state, state;
reg		rec_datH, rec_datSyncH;
reg	[3:0]	bitCell_cntrH;
reg		cntr_resetH;
reg	[7:0]	par_dataH;
reg		shiftH;
reg	[3:0]	recd_bitcntrH;
reg		countH;
reg		rstcountH;
reg		rec_readyH;
reg		rec_readyInH;


wire	[7:0]	rec_dataH;

/////////////////////////////////////////////
//  SEQUENCAL LOGIC                        //
/////////////////////////////////////////////


assign rec_dataH = par_dataH;

//
// synchronize the asynchrnous input
// to the system clock domain
// dual-rank

always @(posedge sys_clk or negedge sys_rst_b)
  if (~sys_rst_b) 
     begin
       rec_datSyncH <= 1;
       rec_datH     <= 1;
     end 
  else
     begin
       rec_datSyncH <= uart_dataH;
       rec_datH     <= rec_datSyncH;
     end


// Bit-cell counter

always @(posedge sys_clk or negedge sys_rst_b)
  if (~sys_rst_b) 
     bitCell_cntrH <= 0;
  else 
     if (cntr_resetH) 
       bitCell_cntrH <= 0;
     else 
       bitCell_cntrH <= bitCell_cntrH + 1;


// Shifte Register to hold the incoming 
// serial data
// LSB is shifted in first
//

always @(posedge sys_clk or negedge sys_rst_b)
  if (~sys_rst_b) 
      par_dataH <= 0;
  else
    if(shiftH)
       begin
         par_dataH[6:0] <= par_dataH[7:1];
         par_dataH[7]   <= rec_sample;
       end


// RECEIVED BIT Counter
// This coutner keeps track of the number of
// bits received

always @(posedge sys_clk or negedge sys_rst_b)
  if (~sys_rst_b) 
      recd_bitcntrH <= 0;
  else
     if (countH)
        recd_bitcntrH <= recd_bitcntrH + 1;
     else 
        if (rstcountH)
           recd_bitcntrH <= 0;

/////////////////////////////////////////////
// state MACHINE                           //
/////////////////////////////////////////////



// state Machine - Next state Assignment

always @(posedge sys_clk or negedge sys_rst_b)
  if (~sys_rst_b) 
     state <= r_START;
  else 
    state <= next_state;


// register the state machine outputs
// to eliminate ciritical-path/glithces

always @(posedge sys_clk or negedge sys_rst_b)
  if (~sys_rst_b) 
     rec_readyH <= 0;
  else 
     rec_readyH <= rec_readyInH;


// state Machine - Next state and Output Decode

always @(state or rec_datH or bitCell_cntrH )
begin
  // default
  next_state  = state;
  cntr_resetH = HI;
  shiftH      = LO;
  countH      = LO;
  rstcountH   = LO;
  rec_readyInH= LO;


case (state)

    R_START: begin
               if (!rec_datH )
                  next_state = R_CENTER;       
               else begin 
                      next_state = R_START;
                      rstcountH  = HI;                  
                      rec_readyInH = HI;                
                    end
              end

   R_CENTER: begin
              if (bitCell_cntrH == 4'h6) 
                 samp0 = rec_regdata;
             else if(bitCell_cntrH==4’h8)
                    samp1 = rec_regdata;
                  else if(bitCell_cntrH==4’hA)            
                       samp2 = rec_regdata;
                        else if(bitCell_cntrH==4’hC)
                                   begin  if（samp0 |samp1 |samp2）  
                                             next_state = R_START;
                                          else   next_state = R_WAIT;    
                                   end                               
                            else         
                              next_state  = R_CENTER;
              end
 
   R_WAIT: begin
	     if (recd_bitcntrH == WORD_LEN)
                     next_state = R_STOP;          
             else    
                    next_state = R_SAMPLE;    
           end
  R_SAMPLE:begin
              if (bitCell_cntrH == 4'h6) 
                      sample[0] = rec_regdata;
              else if(bitCell_cntrH==4’h8)
                        sample[1] = rec_regdata;
                   else if(bitCell_cntrH==4’ha)
                            sample[2] = rec_regdata;         
                        else if(bitCell_cntrH==4’hc)   
                               begin      
                                 rec_sample=(sample[0]&sample[1]) | (sample[1] &sample[2] )| (sample[0] &sample[2]);       
                                 shiftH = HI;                   
                                 countH = HI;                 
	                         next_state = R_WAIT;
	                       end	
                             else     
                                next_state  = R_SAMPLE;
            end

    R_STOP: begin
              next_state   = R_START;
              rec_readyInH  = HI;       
            end
  endcase
end




endmodule