div12.rpt
来自「用VHDL语言实现通用计算器设计」· RPT 代码 · 共 982 行 · 第 1/4 页
RPT
982 行
-- Node name is '|div1:1|divide:divide_component|StageOut3_2' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC6_B19', type is buried
_LC6_B19 = LCELL( _EQ036);
_EQ036 = den2 & _LC1_B17 & !_LC2_B21
# !den2 & !_LC1_B17 & _LC1_B19 & !_LC2_B21
# !den2 & _LC1_B17 & _LC2_B21
# den2 & !_LC1_B17 & _LC1_B19 & _LC2_B21
# _LC1_B17 & !_LC1_B19;
-- Node name is '|div1:1|divide:divide_component|StageOut3_3' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC7_B19', type is buried
_LC7_B19 = LCELL( _EQ037);
_EQ037 = !den3 & _LC3_B19 & _LC4_B19
# den3 & !_LC3_B19 & _LC4_B19;
-- Node name is '|div1:1|divide:divide_component|StageOut4_0' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC5_B23', type is buried
_LC5_B23 = LCELL( _EQ038);
_EQ038 = !_LC5_B19 & num3
# !den0 & num3
# den0 & _LC5_B19 & !num3;
-- Node name is '|div1:1|divide:divide_component|StageOut4_1' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC8_B23', type is buried
_LC8_B23 = LCELL( _EQ039);
_EQ039 = _LC3_B21 & !_LC5_B19
# den1 & _LC2_B23 & !_LC3_B21 & _LC5_B19
# !den1 & !_LC2_B23 & !_LC3_B21 & _LC5_B19
# !den1 & _LC2_B23 & _LC3_B21
# den1 & !_LC2_B23 & _LC3_B21;
-- Node name is '|div1:1|divide:divide_component|StageOut4_2' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC1_B21', type is buried
_LC1_B21 = LCELL( _EQ040);
_EQ040 = !_LC5_B19 & _LC8_B21
# den2 & !_LC7_B21 & _LC8_B21
# !den2 & _LC5_B19 & !_LC7_B21 & !_LC8_B21
# !den2 & _LC7_B21 & _LC8_B21
# den2 & _LC5_B19 & _LC7_B21 & !_LC8_B21;
-- Node name is '|div1:1|divide:divide_component|StageOut4_3' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC2_B19', type is buried
_LC2_B19 = LCELL( _EQ041);
_EQ041 = !_LC5_B19 & _LC6_B19
# den3 & !_LC4_B21 & _LC6_B19
# !den3 & !_LC4_B21 & _LC5_B19 & !_LC6_B19
# !den3 & _LC4_B21 & _LC6_B19
# den3 & _LC4_B21 & _LC5_B19 & !_LC6_B19;
-- Node name is '|div1:1|divide:divide_component|StageOut5_0' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = LCELL( _EQ042);
_EQ042 = !_LC3_B18 & num2
# !den0 & num2
# den0 & _LC3_B18 & !num2;
-- Node name is '|div1:1|divide:divide_component|StageOut5_1' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = LCELL( _EQ043);
_EQ043 = !_LC3_B18 & _LC5_B23
# !den1 & _LC3_B18 & !_LC5_B23 & !_LC6_B23
# den1 & _LC3_B18 & !_LC5_B23 & _LC6_B23
# !den1 & _LC5_B23 & _LC6_B23
# den1 & _LC5_B23 & !_LC6_B23;
-- Node name is '|div1:1|divide:divide_component|StageOut5_2' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = LCELL( _EQ044);
_EQ044 = !_LC3_B18 & _LC8_B23
# !den2 & _LC7_B23 & _LC8_B23
# den2 & !_LC7_B23 & _LC8_B23
# den2 & _LC3_B18 & _LC7_B23 & !_LC8_B23
# !den2 & _LC3_B18 & !_LC7_B23 & !_LC8_B23;
-- Node name is '|div1:1|divide:divide_component|StageOut5_3' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC4_B18', type is buried
_LC4_B18 = LCELL( _EQ045);
_EQ045 = _LC1_B21 & !_LC3_B18
# den3 & _LC1_B21 & !_LC1_B23
# !den3 & !_LC1_B21 & !_LC1_B23 & _LC3_B18
# !den3 & _LC1_B21 & _LC1_B23
# den3 & !_LC1_B21 & _LC1_B23 & _LC3_B18;
-- Node name is '|div1:1|divide:divide_component|StageOut6_0' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = LCELL( _EQ046);
_EQ046 = !_LC1_B18 & num1
# !den0 & num1
# den0 & _LC1_B18 & !num1;
-- Node name is '|div1:1|divide:divide_component|StageOut6_1' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC8_B13', type is buried
_LC8_B13 = LCELL( _EQ047);
_EQ047 = _LC1_B16 & !_LC1_B18
# den1 & !_LC1_B16 & _LC1_B18 & _LC4_B13
# !den1 & !_LC1_B16 & _LC1_B18 & !_LC4_B13
# !den1 & _LC1_B16 & _LC4_B13
# den1 & _LC1_B16 & !_LC4_B13;
-- Node name is '|div1:1|divide:divide_component|StageOut6_2' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = LCELL( _EQ048);
_EQ048 = !_LC1_B18 & _LC4_B23
# den2 & _LC1_B18 & _LC2_B13 & !_LC4_B23
# !den2 & _LC1_B18 & !_LC2_B13 & !_LC4_B23
# !den2 & _LC2_B13 & _LC4_B23
# den2 & !_LC2_B13 & _LC4_B23;
-- Node name is '|div1:1|divide:divide_component|StageOut6_3' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC7_B18', type is buried
_LC7_B18 = LCELL( _EQ049);
_EQ049 = !_LC1_B18 & _LC3_B23
# !den3 & _LC2_B18 & _LC3_B23
# den3 & _LC1_B18 & _LC2_B18 & !_LC3_B23
# den3 & !_LC2_B18 & _LC3_B23
# !den3 & _LC1_B18 & !_LC2_B18 & !_LC3_B23;
-- Node name is '|div1:1|divide:divide_component|StageOut7_0' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = LCELL( _EQ050);
_EQ050 = !_LC8_B18 & num0
# !den0 & num0
# den0 & _LC8_B18 & !num0;
-- Node name is '|div1:1|divide:divide_component|StageOut7_1' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = LCELL( _EQ051);
_EQ051 = _LC5_B13 & !_LC8_B18
# den1 & _LC4_A22 & !_LC5_B13 & _LC8_B18
# !den1 & !_LC4_A22 & !_LC5_B13 & _LC8_B18
# !den1 & _LC4_A22 & _LC5_B13
# den1 & !_LC4_A22 & _LC5_B13;
-- Node name is '|div1:1|divide:divide_component|StageOut7_2' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC7_B13', type is buried
_LC7_B13 = LCELL( _EQ052);
_EQ052 = _LC8_B13 & !_LC8_B18
# den2 & _LC6_B13 & !_LC8_B13 & _LC8_B18
# !den2 & !_LC6_B13 & !_LC8_B13 & _LC8_B18
# !den2 & _LC6_B13 & _LC8_B13
# den2 & !_LC6_B13 & _LC8_B13;
-- Node name is '|div1:1|divide:divide_component|StageOut7_3' from file "divide.tdf" line 86, column 10
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = LCELL( _EQ053);
_EQ053 = _LC5_B18 & !_LC8_B18
# den3 & !_LC1_B13 & _LC5_B18
# !den3 & !_LC1_B13 & !_LC5_B18 & _LC8_B18
# !den3 & _LC1_B13 & _LC5_B18
# den3 & _LC1_B13 & !_LC5_B18 & _LC8_B18;
Project Information c:\work\div12.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:04
Database Builder 00:00:00
Logic Synthesizer 00:00:05
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:14
Memory Allocated
-----------------
Peak memory allocated during compilation = 29,031K
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