div12.rpt
来自「用VHDL语言实现通用计算器设计」· RPT 代码 · 共 982 行 · 第 1/4 页
RPT
982 行
42 - - - -- INPUT 0 0 0 16 den0
44 - - - -- INPUT 0 0 0 15 den1
2 - - - -- INPUT 0 0 0 13 den2
84 - - - -- INPUT 0 0 0 12 den3
17 - - A -- INPUT 0 0 0 2 num0
80 - - - 23 INPUT 0 0 0 2 num1
43 - - - -- INPUT 0 0 0 2 num2
51 - - - 18 INPUT 0 0 0 2 num3
47 - - - 14 INPUT 0 0 0 2 num4
1 - - - -- INPUT 0 0 0 2 num5
24 - - B -- INPUT 0 0 0 2 num6
22 - - B -- INPUT 0 0 0 2 num7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\work\div12.rpt
div12
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
70 - - A -- OUTPUT 0 1 0 0 quo0
21 - - B -- OUTPUT 0 1 0 0 quo1
23 - - B -- OUTPUT 0 1 0 0 quo2
65 - - B -- OUTPUT 0 1 0 0 quo3
67 - - B -- OUTPUT 0 1 0 0 quo4
25 - - B -- OUTPUT 0 1 0 0 quo5
64 - - B -- OUTPUT 0 1 0 0 quo6
48 - - - 15 OUTPUT 0 1 0 0 quo7
73 - - A -- OUTPUT 0 1 0 0 rem0
66 - - B -- OUTPUT 0 1 0 0 rem1
83 - - - 13 OUTPUT 0 1 0 0 rem2
50 - - - 17 OUTPUT 0 1 0 0 rem3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\work\div12.rpt
div12
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - B 16 OR2 2 0 0 2 |div1:1|divide:divide_component|lpm_add_sub:67|addcore:adder|pcarry0
- 3 - B 17 OR2 2 0 0 2 |div1:1|divide:divide_component|lpm_add_sub:83|addcore:adder|pcarry0
- 2 - B 17 OR2 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:83|addcore:adder|pcarry1
- 6 - B 21 AND2 ! 2 0 0 2 |div1:1|divide:divide_component|lpm_add_sub:102|addcore:adder|pcarry0
- 2 - B 21 OR2 ! 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:102|addcore:adder|pcarry1
- 3 - B 19 OR2 ! 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:102|addcore:adder|pcarry2
- 1 - B 19 OR2 1 2 1 3 |div1:1|divide:divide_component|lpm_add_sub:102|addcore:adder|pcarry3
- 2 - B 23 OR2 2 0 0 2 |div1:1|divide:divide_component|lpm_add_sub:124|addcore:adder|pcarry0
- 7 - B 21 OR2 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:124|addcore:adder|pcarry1
- 4 - B 21 OR2 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:124|addcore:adder|pcarry2
- 5 - B 19 OR2 1 3 1 4 |div1:1|divide:divide_component|lpm_add_sub:124|addcore:adder|pcarry4
- 6 - B 23 OR2 2 0 0 2 |div1:1|divide:divide_component|lpm_add_sub:149|addcore:adder|pcarry0
- 7 - B 23 OR2 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:149|addcore:adder|pcarry1
- 1 - B 23 OR2 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:149|addcore:adder|pcarry2
- 3 - B 18 OR2 1 3 1 4 |div1:1|divide:divide_component|lpm_add_sub:149|addcore:adder|pcarry4
- 4 - B 13 OR2 2 0 0 2 |div1:1|divide:divide_component|lpm_add_sub:174|addcore:adder|pcarry0
- 2 - B 13 OR2 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:174|addcore:adder|pcarry1
- 2 - B 18 OR2 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:174|addcore:adder|pcarry2
- 1 - B 18 OR2 1 3 1 4 |div1:1|divide:divide_component|lpm_add_sub:174|addcore:adder|pcarry4
- 4 - A 22 OR2 2 0 0 2 |div1:1|divide:divide_component|lpm_add_sub:199|addcore:adder|pcarry0
- 6 - B 13 OR2 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:199|addcore:adder|pcarry1
- 1 - B 13 OR2 1 2 0 2 |div1:1|divide:divide_component|lpm_add_sub:199|addcore:adder|pcarry2
- 8 - B 18 OR2 1 3 1 4 |div1:1|divide:divide_component|lpm_add_sub:199|addcore:adder|pcarry4
- 5 - B 16 AND2 s 2 0 0 3 |div1:1|divide:divide_component|selnose0_0~1
- 2 - B 16 OR2 ! 3 1 1 1 |div1:1|divide:divide_component|selnose0_0
- 7 - B 16 OR2 ! 1 3 1 1 |div1:1|divide:divide_component|selnose1_1
- 8 - B 19 OR2 ! 2 2 1 3 |div1:1|divide:divide_component|selnose2_2
- 6 - B 16 LCELL 2 1 0 2 |div1:1|divide:divide_component|StageOut0_0
- 4 - B 16 LCELL 2 1 0 2 |div1:1|divide:divide_component|StageOut1_0
- 3 - B 16 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut1_1
- 5 - B 21 LCELL 2 1 0 2 |div1:1|divide:divide_component|StageOut2_0
- 1 - B 17 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut2_1
- 4 - B 19 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut2_2
- 3 - B 21 LCELL 2 1 0 2 |div1:1|divide:divide_component|StageOut3_0
- 8 - B 21 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut3_1
- 6 - B 19 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut3_2
- 7 - B 19 LCELL 1 2 0 1 |div1:1|divide:divide_component|StageOut3_3
- 5 - B 23 LCELL 2 1 0 2 |div1:1|divide:divide_component|StageOut4_0
- 8 - B 23 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut4_1
- 1 - B 21 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut4_2
- 2 - B 19 LCELL 1 3 0 1 |div1:1|divide:divide_component|StageOut4_3
- 1 - B 16 LCELL 2 1 0 2 |div1:1|divide:divide_component|StageOut5_0
- 4 - B 23 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut5_1
- 3 - B 23 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut5_2
- 4 - B 18 LCELL 1 3 0 1 |div1:1|divide:divide_component|StageOut5_3
- 5 - B 13 LCELL 2 1 0 2 |div1:1|divide:divide_component|StageOut6_0
- 8 - B 13 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut6_1
- 5 - B 18 LCELL 1 3 0 2 |div1:1|divide:divide_component|StageOut6_2
- 7 - B 18 LCELL 1 3 0 1 |div1:1|divide:divide_component|StageOut6_3
- 1 - A 22 LCELL 2 1 1 0 |div1:1|divide:divide_component|StageOut7_0
- 3 - B 13 LCELL 1 3 1 0 |div1:1|divide:divide_component|StageOut7_1
- 7 - B 13 LCELL 1 3 1 0 |div1:1|divide:divide_component|StageOut7_2
- 6 - B 18 LCELL 1 3 1 0 |div1:1|divide:divide_component|StageOut7_3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\work\div12.rpt
div12
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 2/ 48( 4%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
B: 11/ 96( 11%) 0/ 48( 0%) 19/ 48( 39%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\work\div12.rpt
div12
** EQUATIONS **
den0 : INPUT;
den1 : INPUT;
den2 : INPUT;
den3 : INPUT;
num0 : INPUT;
num1 : INPUT;
num2 : INPUT;
num3 : INPUT;
num4 : INPUT;
num5 : INPUT;
num6 : INPUT;
num7 : INPUT;
-- Node name is 'quo0'
-- Equation name is 'quo0', type is output
quo0 = _LC8_B18;
-- Node name is 'quo1'
-- Equation name is 'quo1', type is output
quo1 = _LC1_B18;
-- Node name is 'quo2'
-- Equation name is 'quo2', type is output
quo2 = _LC3_B18;
-- Node name is 'quo3'
-- Equation name is 'quo3', type is output
quo3 = _LC5_B19;
-- Node name is 'quo4'
-- Equation name is 'quo4', type is output
quo4 = _LC1_B19;
-- Node name is 'quo5'
-- Equation name is 'quo5', type is output
quo5 = !_LC8_B19;
-- Node name is 'quo6'
-- Equation name is 'quo6', type is output
quo6 = !_LC7_B16;
-- Node name is 'quo7'
-- Equation name is 'quo7', type is output
quo7 = !_LC2_B16;
-- Node name is 'rem0'
-- Equation name is 'rem0', type is output
rem0 = _LC1_A22;
-- Node name is 'rem1'
-- Equation name is 'rem1', type is output
rem1 = _LC3_B13;
-- Node name is 'rem2'
-- Equation name is 'rem2', type is output
rem2 = _LC7_B13;
-- Node name is 'rem3'
-- Equation name is 'rem3', type is output
rem3 = _LC6_B18;
-- Node name is '|div1:1|divide:divide_component|lpm_add_sub:67|addcore:adder|pcarry0' from file "addcore.tdf" line 308, column 64
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = LCELL( _EQ001);
_EQ001 = num6
# !den0;
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