mul12.rpt
来自「用VHDL语言实现通用计算器设计」· RPT 代码 · 共 731 行 · 第 1/3 页
RPT
731 行
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:68' from file "csa_cell.tdf" line 22, column 26
-- Equation name is '_LC8_B4', type is buried
_LC8_B4 = LCELL( _EQ012);
_EQ012 = adata0 & !adata1 & bdata1
# adata0 & !bdata0 & bdata1
# adata1 & bdata0 & !bdata1
# !adata0 & adata1 & bdata0;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~77~1' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC2_B4', type is buried
-- synthesized logic cell
_LC2_B4 = LCELL( _EQ013);
_EQ013 = adata2 & bdata0 & !bdata2
# !adata0 & adata2 & bdata0
# adata0 & !adata2 & bdata2
# adata0 & !bdata0 & bdata2;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~78~1' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC4_B2', type is buried
-- synthesized logic cell
_LC4_B2 = LCELL( _EQ014);
_EQ014 = adata3 & bdata0 & !bdata2
# !adata1 & adata3 & bdata0
# adata1 & !adata3 & bdata2
# adata1 & !bdata0 & bdata2;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:78' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ015);
_EQ015 = adata2 & bdata1 & !_LC4_B2
# !adata2 & _LC4_B2
# !bdata1 & _LC4_B2;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:79' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = LCELL( _EQ016);
_EQ016 = !adata2 & adata3 & bdata1
# adata3 & bdata1 & !bdata2
# adata2 & !adata3 & bdata2
# adata2 & !bdata1 & bdata2;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:84' from file "csa_cell.tdf" line 23, column 27
-- Equation name is '_LC5_B6', type is buried
_LC5_B6 = LCELL( _EQ017);
_EQ017 = adata0 & adata1 & bdata0 & bdata1;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:143' from file "csa_cell.tdf" line 25, column 31
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ018);
_EQ018 = adata2 & adata3 & bdata1 & bdata2;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~149~1' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC4_B4', type is buried
-- synthesized logic cell
_LC4_B4 = LCELL( _EQ019);
_EQ019 = adata1 & adata2 & bdata0 & bdata1;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~149~2' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC5_B4', type is buried
-- synthesized logic cell
_LC5_B4 = LCELL( _EQ020);
_EQ020 = adata1 & bdata1
# adata2 & bdata0;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:149' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = LCELL( _EQ021);
_EQ021 = _LC4_B4
# adata0 & bdata2 & _LC5_B4;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~150~1' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC5_B2', type is buried
-- synthesized logic cell
_LC5_B2 = LCELL( _EQ022);
_EQ022 = adata2 & adata3 & bdata0 & bdata1;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~150~2' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC6_B2', type is buried
-- synthesized logic cell
_LC6_B2 = LCELL( _EQ023);
_EQ023 = adata2 & bdata1
# adata3 & bdata0;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:150' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC7_B2', type is buried
_LC7_B2 = LCELL( _EQ024);
_EQ024 = _LC5_B2
# adata1 & bdata2 & _LC6_B2;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_B6', type is buried
_LC4_B6 = LCELL( _EQ025);
_EQ025 = _LC6_B6 & _LC7_B6 & _LC8_B6
# _LC2_B2 & _LC6_B6 & _LC7_B6
# _LC2_B2 & _LC8_B6;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = LCELL( _EQ026);
_EQ026 = _LC3_B2 & _LC4_B6
# _LC3_B4 & _LC4_B6
# _LC3_B2 & _LC3_B4;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = LCELL( _EQ027);
_EQ027 = adata3 & bdata3 & _LC2_B7
# _LC2_B7 & _LC7_B7
# adata3 & bdata3 & _LC7_B7;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:126' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = LCELL( _EQ028);
_EQ028 = !_LC6_B6 & _LC7_B6
# _LC6_B6 & !_LC7_B6;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:127' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = LCELL( _EQ029);
_EQ029 = _LC2_B2 & _LC6_B6 & _LC7_B6 & _LC8_B6
# !_LC2_B2 & _LC6_B6 & _LC7_B6 & !_LC8_B6
# !_LC2_B2 & !_LC7_B6 & _LC8_B6
# !_LC2_B2 & !_LC6_B6 & _LC8_B6
# _LC2_B2 & !_LC7_B6 & !_LC8_B6
# _LC2_B2 & !_LC6_B6 & !_LC8_B6;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:128' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ030);
_EQ030 = _LC3_B2 & _LC3_B4 & _LC4_B6
# !_LC3_B2 & !_LC3_B4 & _LC4_B6
# _LC3_B2 & !_LC3_B4 & !_LC4_B6
# !_LC3_B2 & _LC3_B4 & !_LC4_B6;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:129' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = LCELL( _EQ031);
_EQ031 = adata3 & bdata3 & _LC2_B7 & _LC7_B7
# !adata3 & _LC2_B7 & !_LC7_B7
# !bdata3 & _LC2_B7 & !_LC7_B7
# !adata3 & !_LC2_B7 & _LC7_B7
# !bdata3 & !_LC2_B7 & _LC7_B7
# adata3 & bdata3 & !_LC2_B7 & !_LC7_B7;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node0_0' from file "multcore.tdf" line 781, column 38
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ032);
_EQ032 = adata0 & bdata0;
Project Information c:\work\mul12.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 29,356K
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