mul12.rpt
来自「用VHDL语言实现通用计算器设计」· RPT 代码 · 共 731 行 · 第 1/3 页
RPT
731 行
23 - - B -- OUTPUT 0 1 0 0 resu3
21 - - B -- OUTPUT 0 1 0 0 resu4
25 - - B -- OUTPUT 0 1 0 0 resu5
66 - - B -- OUTPUT 0 1 0 0 resu6
67 - - B -- OUTPUT 0 1 0 0 resu7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\work\mul12.rpt
mul12
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 06 OR2 2 2 1 0 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:74
- 7 - B 06 OR2 2 2 0 3 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:84
- 2 - B 02 OR2 2 2 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:85
- 7 - B 04 OR2 s 4 0 0 1 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~86~1
- 3 - B 04 OR2 2 1 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:86
- 6 - B 06 OR2 2 2 0 3 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:92
- 8 - B 06 OR2 2 2 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:165
- 3 - B 02 OR2 2 2 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:166
- 4 - B 07 AND2 s 3 0 0 1 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~167~1
- 6 - B 07 OR2 s 3 1 0 1 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~167~2
- 7 - B 07 OR2 2 2 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:167
- 8 - B 04 OR2 4 0 1 0 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:68
- 2 - B 04 OR2 s 4 0 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~77~1
- 4 - B 02 OR2 s 4 0 0 1 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~78~1
- 1 - B 02 OR2 2 1 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:78
- 8 - B 02 OR2 4 0 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:79
- 5 - B 06 AND2 4 0 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:84
- 5 - B 07 AND2 4 0 0 1 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:143
- 4 - B 04 AND2 s 4 0 0 1 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~149~1
- 5 - B 04 OR2 s 4 0 0 1 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~149~2
- 1 - B 04 OR2 2 2 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:149
- 5 - B 02 AND2 s 4 0 0 1 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~150~1
- 6 - B 02 OR2 s 4 0 0 1 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~150~2
- 7 - B 02 OR2 2 2 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:150
- 4 - B 06 OR2 0 4 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry4
- 2 - B 07 OR2 0 3 0 2 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry5
- 1 - B 07 OR2 2 2 1 0 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry6
- 3 - B 06 OR2 0 2 1 0 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:126
- 1 - B 06 OR2 0 4 1 0 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:127
- 8 - B 07 OR2 0 3 1 0 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:128
- 3 - B 07 OR2 2 2 1 0 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:129
- 6 - B 04 AND2 2 0 1 0 |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node0_0
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\work\mul12.rpt
mul12
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 10/ 48( 20%) 0/ 48( 0%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\work\mul12.rpt
mul12
** EQUATIONS **
adata0 : INPUT;
adata1 : INPUT;
adata2 : INPUT;
adata3 : INPUT;
bdata0 : INPUT;
bdata1 : INPUT;
bdata2 : INPUT;
bdata3 : INPUT;
-- Node name is 'resu0'
-- Equation name is 'resu0', type is output
resu0 = _LC6_B4;
-- Node name is 'resu1'
-- Equation name is 'resu1', type is output
resu1 = _LC8_B4;
-- Node name is 'resu2'
-- Equation name is 'resu2', type is output
resu2 = _LC2_B6;
-- Node name is 'resu3'
-- Equation name is 'resu3', type is output
resu3 = _LC3_B6;
-- Node name is 'resu4'
-- Equation name is 'resu4', type is output
resu4 = _LC1_B6;
-- Node name is 'resu5'
-- Equation name is 'resu5', type is output
resu5 = _LC8_B7;
-- Node name is 'resu6'
-- Equation name is 'resu6', type is output
resu6 = _LC3_B7;
-- Node name is 'resu7'
-- Equation name is 'resu7', type is output
resu7 = _LC1_B7;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:74' from file "csa_cell.tdf" line 22, column 26
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = LCELL( _EQ001);
_EQ001 = adata1 & bdata1 & _LC2_B4 & _LC5_B6
# !bdata1 & !_LC2_B4 & _LC5_B6
# !adata1 & !_LC2_B4 & _LC5_B6
# !bdata1 & _LC2_B4 & !_LC5_B6
# !adata1 & _LC2_B4 & !_LC5_B6
# adata1 & bdata1 & !_LC2_B4 & !_LC5_B6;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:84' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC7_B6', type is buried
_LC7_B6 = LCELL( _EQ002);
_EQ002 = adata0 & bdata3 & _LC1_B2 & _LC1_B4
# !bdata3 & _LC1_B2 & !_LC1_B4
# !adata0 & _LC1_B2 & !_LC1_B4
# !bdata3 & !_LC1_B2 & _LC1_B4
# !adata0 & !_LC1_B2 & _LC1_B4
# adata0 & bdata3 & !_LC1_B2 & !_LC1_B4;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:85' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = LCELL( _EQ003);
_EQ003 = adata1 & bdata3 & _LC7_B2 & _LC8_B2
# !bdata3 & _LC7_B2 & !_LC8_B2
# !adata1 & _LC7_B2 & !_LC8_B2
# !bdata3 & !_LC7_B2 & _LC8_B2
# !adata1 & !_LC7_B2 & _LC8_B2
# adata1 & bdata3 & !_LC7_B2 & !_LC8_B2;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~86~1' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC7_B4', type is buried
-- synthesized logic cell
_LC7_B4 = LCELL( _EQ004);
_EQ004 = adata3 & !bdata1 & bdata2
# !adata2 & adata3 & bdata2;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:86' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC3_B4', type is buried
_LC3_B4 = LCELL( _EQ005);
_EQ005 = adata2 & bdata3 & !_LC7_B4
# !bdata3 & _LC7_B4
# !adata2 & _LC7_B4;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:92' from file "csa_cell.tdf" line 23, column 27
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = LCELL( _EQ006);
_EQ006 = adata1 & bdata1 & !_LC2_B4 & _LC5_B6
# !bdata1 & _LC2_B4 & _LC5_B6
# !adata1 & _LC2_B4 & _LC5_B6;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:165' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC8_B6', type is buried
_LC8_B6 = LCELL( _EQ007);
_EQ007 = _LC1_B2 & _LC1_B4
# adata0 & bdata3 & _LC1_B2
# adata0 & bdata3 & _LC1_B4;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:166' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = LCELL( _EQ008);
_EQ008 = _LC7_B2 & _LC8_B2
# adata1 & bdata3 & _LC7_B2
# adata1 & bdata3 & _LC8_B2;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~167~1' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC4_B7', type is buried
-- synthesized logic cell
_LC4_B7 = LCELL( _EQ009);
_EQ009 = adata2 & !bdata1 & bdata3;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~167~2' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC6_B7', type is buried
-- synthesized logic cell
_LC6_B7 = LCELL( _EQ010);
_EQ010 = adata3 & bdata2 & _LC5_B7
# bdata3 & _LC5_B7;
-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:167' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = LCELL( _EQ011);
_EQ011 = adata3 & bdata2 & _LC4_B7
# _LC6_B7;
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