half_adder.fit.summary

来自「用VHDL语言实现半加器。已经通过编译和仿真」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Wed Feb 25 10:16:32 2009
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
Revision Name : half_adder
Top-level Entity Name : half_adder
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
Total logic elements : 2 / 12,060 ( < 1 % )
Total pins : 8 / 173 ( 5 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )