half_adder.hier_info

用VHDL语言实现半加器。已经通过编译和仿真

|half_adder
a => d.IN0
a => c.IN0
b => d.IN1
b => c.IN1
s <= s~0.DB_MAX_OUTPUT_PORT_TYPE
co <= d.DB_MAX_OUTPUT_PORT_TYPE
VGA[0] <= <VCC>
VGA[1] <= <GND>
VGA[2] <= <GND>
VGA[3] <= <GND>