half_adder.map.summary

用VHDL语言实现半加器。已经通过编译和仿真

Analysis & Synthesis Status : Successful - Wed Feb 25 10:16:26 2009
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
Revision Name : half_adder
Top-level Entity Name : half_adder
Family : Cyclone
Total logic elements : 2
Total pins : 8
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0