half_adder_v.sdo

用VHDL语言实现半加器。已经通过编译和仿真

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1C12Q240C8 Package PQFP240
// 

// 
// This SDF file should be used for VCS only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "half_adder")
  (DATE "02/25/2009 10:16:39")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE b\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1475:1475:1475) (1475:1475:1475))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE a\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1475:1475:1475) (1475:1475:1475))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE s\~2.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (5820:5820:5820) (5820:5820:5820))
        (PORT datad (5401:5401:5401) (5401:5401:5401))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE d.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (5820:5820:5820) (5820:5820:5820))
        (PORT datad (5400:5400:5400) (5400:5400:5400))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE s\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1674:1674:1674) (1674:1674:1674))
        (IOPATH datain padio (2124:2124:2124) (2124:2124:2124))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE co\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (1671:1671:1671) (1671:1671:1671))
        (IOPATH datain padio (2124:2124:2124) (2124:2124:2124))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE VGA\[0\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH datain padio (2124:2124:2124) (2124:2124:2124))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE VGA\[1\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH datain padio (2124:2124:2124) (2124:2124:2124))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE VGA\[2\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH datain padio (2124:2124:2124) (2124:2124:2124))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE VGA\[3\]\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH datain padio (2124:2124:2124) (2124:2124:2124))
      )
    )
  )
)