half_adder.vo

用VHDL语言实现半加器。已经通过编译和仿真

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version"

// DATE "02/25/2009 10:16:39"

// 
// Device: Altera EP1C12Q240C8 Package PQFP240
// 

// 
// This Verilog file should be used for VCS only
// 

`timescale 1 ps/ 1 ps

module half_adder (
	a,
	b,
	s,
	co,
	VGA);
input 	a;
input 	b;
output 	s;
output 	co;
output 	[3:0] VGA;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("half_adder_v.sdo");
// synopsys translate_on

wire \b~combout ;
wire \a~combout ;
wire \s~2_combout ;
wire \d~combout ;


// atom is at PIN_104
cyclone_io \b~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\b~combout ),
	.regout(),
	.padio(b));
// synopsys translate_off
defparam \b~I .input_async_reset = "none";
defparam \b~I .input_power_up = "low";
defparam \b~I .input_register_mode = "none";
defparam \b~I .input_sync_reset = "none";
defparam \b~I .oe_async_reset = "none";
defparam \b~I .oe_power_up = "low";
defparam \b~I .oe_register_mode = "none";
defparam \b~I .oe_sync_reset = "none";
defparam \b~I .operation_mode = "input";
defparam \b~I .output_async_reset = "none";
defparam \b~I .output_power_up = "low";
defparam \b~I .output_register_mode = "none";
defparam \b~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_105
cyclone_io \a~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\a~combout ),
	.regout(),
	.padio(a));
// synopsys translate_off
defparam \a~I .input_async_reset = "none";
defparam \a~I .input_power_up = "low";
defparam \a~I .input_register_mode = "none";
defparam \a~I .input_sync_reset = "none";
defparam \a~I .oe_async_reset = "none";
defparam \a~I .oe_power_up = "low";
defparam \a~I .oe_register_mode = "none";
defparam \a~I .oe_sync_reset = "none";
defparam \a~I .operation_mode = "input";
defparam \a~I .output_async_reset = "none";
defparam \a~I .output_power_up = "low";
defparam \a~I .output_register_mode = "none";
defparam \a~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X47_Y4_N4
cyclone_lcell \s~2 (
// Equation(s):
// \s~2_combout  = \b~combout  $ (\a~combout )

	.clk(gnd),
	.dataa(vcc),
	.datab(\b~combout ),
	.datac(vcc),
	.datad(\a~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\s~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \s~2 .lut_mask = "33cc";
defparam \s~2 .operation_mode = "normal";
defparam \s~2 .output_mode = "comb_only";
defparam \s~2 .register_cascade_mode = "off";
defparam \s~2 .sum_lutc_input = "datac";
defparam \s~2 .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X47_Y4_N2
cyclone_lcell d(
// Equation(s):
// \d~combout  = \b~combout  & (\a~combout )

	.clk(gnd),
	.dataa(vcc),
	.datab(\b~combout ),
	.datac(vcc),
	.datad(\a~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\d~combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam d.lut_mask = "cc00";
defparam d.operation_mode = "normal";
defparam d.output_mode = "comb_only";
defparam d.register_cascade_mode = "off";
defparam d.sum_lutc_input = "datac";
defparam d.synch_mode = "off";
// synopsys translate_on

// atom is at PIN_133
cyclone_io \s~I (
	.datain(\s~2_combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(s));
// synopsys translate_off
defparam \s~I .input_async_reset = "none";
defparam \s~I .input_power_up = "low";
defparam \s~I .input_register_mode = "none";
defparam \s~I .input_sync_reset = "none";
defparam \s~I .oe_async_reset = "none";
defparam \s~I .oe_power_up = "low";
defparam \s~I .oe_register_mode = "none";
defparam \s~I .oe_sync_reset = "none";
defparam \s~I .operation_mode = "output";
defparam \s~I .output_async_reset = "none";
defparam \s~I .output_power_up = "low";
defparam \s~I .output_register_mode = "none";
defparam \s~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_132
cyclone_io \co~I (
	.datain(\d~combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(co));
// synopsys translate_off
defparam \co~I .input_async_reset = "none";
defparam \co~I .input_power_up = "low";
defparam \co~I .input_register_mode = "none";
defparam \co~I .input_sync_reset = "none";
defparam \co~I .oe_async_reset = "none";
defparam \co~I .oe_power_up = "low";
defparam \co~I .oe_register_mode = "none";
defparam \co~I .oe_sync_reset = "none";
defparam \co~I .operation_mode = "output";
defparam \co~I .output_async_reset = "none";
defparam \co~I .output_power_up = "low";
defparam \co~I .output_register_mode = "none";
defparam \co~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_162
cyclone_io \VGA[0]~I (
	.datain(vcc),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(VGA[0]));
// synopsys translate_off
defparam \VGA[0]~I .input_async_reset = "none";
defparam \VGA[0]~I .input_power_up = "low";
defparam \VGA[0]~I .input_register_mode = "none";
defparam \VGA[0]~I .input_sync_reset = "none";
defparam \VGA[0]~I .oe_async_reset = "none";
defparam \VGA[0]~I .oe_power_up = "low";
defparam \VGA[0]~I .oe_register_mode = "none";
defparam \VGA[0]~I .oe_sync_reset = "none";
defparam \VGA[0]~I .operation_mode = "output";
defparam \VGA[0]~I .output_async_reset = "none";
defparam \VGA[0]~I .output_power_up = "low";
defparam \VGA[0]~I .output_register_mode = "none";
defparam \VGA[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_161
cyclone_io \VGA[1]~I (
	.datain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(VGA[1]));
// synopsys translate_off
defparam \VGA[1]~I .input_async_reset = "none";
defparam \VGA[1]~I .input_power_up = "low";
defparam \VGA[1]~I .input_register_mode = "none";
defparam \VGA[1]~I .input_sync_reset = "none";
defparam \VGA[1]~I .oe_async_reset = "none";
defparam \VGA[1]~I .oe_power_up = "low";
defparam \VGA[1]~I .oe_register_mode = "none";
defparam \VGA[1]~I .oe_sync_reset = "none";
defparam \VGA[1]~I .operation_mode = "output";
defparam \VGA[1]~I .output_async_reset = "none";
defparam \VGA[1]~I .output_power_up = "low";
defparam \VGA[1]~I .output_register_mode = "none";
defparam \VGA[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_164
cyclone_io \VGA[2]~I (
	.datain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(VGA[2]));
// synopsys translate_off
defparam \VGA[2]~I .input_async_reset = "none";
defparam \VGA[2]~I .input_power_up = "low";
defparam \VGA[2]~I .input_register_mode = "none";
defparam \VGA[2]~I .input_sync_reset = "none";
defparam \VGA[2]~I .oe_async_reset = "none";
defparam \VGA[2]~I .oe_power_up = "low";
defparam \VGA[2]~I .oe_register_mode = "none";
defparam \VGA[2]~I .oe_sync_reset = "none";
defparam \VGA[2]~I .operation_mode = "output";
defparam \VGA[2]~I .output_async_reset = "none";
defparam \VGA[2]~I .output_power_up = "low";
defparam \VGA[2]~I .output_register_mode = "none";
defparam \VGA[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_163
cyclone_io \VGA[3]~I (
	.datain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.padio(VGA[3]));
// synopsys translate_off
defparam \VGA[3]~I .input_async_reset = "none";
defparam \VGA[3]~I .input_power_up = "low";
defparam \VGA[3]~I .input_register_mode = "none";
defparam \VGA[3]~I .input_sync_reset = "none";
defparam \VGA[3]~I .oe_async_reset = "none";
defparam \VGA[3]~I .oe_power_up = "low";
defparam \VGA[3]~I .oe_register_mode = "none";
defparam \VGA[3]~I .oe_sync_reset = "none";
defparam \VGA[3]~I .operation_mode = "output";
defparam \VGA[3]~I .output_async_reset = "none";
defparam \VGA[3]~I .output_power_up = "low";
defparam \VGA[3]~I .output_register_mode = "none";
defparam \VGA[3]~I .output_sync_reset = "none";
// synopsys translate_on

endmodule