half_adder.map.eqn

用VHDL语言实现半加器。已经通过编译和仿真

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--A1L6 is s~2
--operation mode is normal

A1L6 = b $ a;


--d is d
--operation mode is normal

d = b & a;


--b is b
--operation mode is input

b = INPUT();


--a is a
--operation mode is input

a = INPUT();


--s is s
--operation mode is output

s = OUTPUT(A1L6);


--co is co
--operation mode is output

co = OUTPUT(d);


--VGA[0] is VGA[0]
--operation mode is output

VGA[0] = OUTPUT(VCC);


--VGA[1] is VGA[1]
--operation mode is output

VGA[1] = OUTPUT(GND);


--VGA[2] is VGA[2]
--operation mode is output

VGA[2] = OUTPUT(GND);


--VGA[3] is VGA[3]
--operation mode is output

VGA[3] = OUTPUT(GND);