seqdet2.smp_dump.txt

状态机实现序列检测VerilogHDL及其仿真

State Machine - |seqdet2|state
Name state.H state.L state.A state.B state.J state.C state.K state.D state.E state.F state.G state.I state.IDLE 
state.IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 
state.I 0 0 0 0 0 0 0 0 0 0 0 1 1 
state.G 0 0 0 0 0 0 0 0 0 0 1 0 1 
state.F 0 0 0 0 0 0 0 0 0 1 0 0 1 
state.E 0 0 0 0 0 0 0 0 1 0 0 0 1 
state.D 0 0 0 0 0 0 0 1 0 0 0 0 1 
state.K 0 0 0 0 0 0 1 0 0 0 0 0 1 
state.C 0 0 0 0 0 1 0 0 0 0 0 0 1 
state.J 0 0 0 0 1 0 0 0 0 0 0 0 1 
state.B 0 0 0 1 0 0 0 0 0 0 0 0 1 
state.A 0 0 1 0 0 0 0 0 0 0 0 0 1 
state.L 0 1 0 0 0 0 0 0 0 0 0 0 1 
state.H 1 0 0 0 0 0 0 0 0 0 0 0 1