seqdet2.eda.qmsg

状态机实现序列检测VerilogHDL及其仿真

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 22 16:39:16 2009 " "Info: Processing started: Sun Feb 22 16:39:16 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off seqdet2 -c seqdet2 " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off seqdet2 -c seqdet2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "seqdet2.vo seqdet2_v.sdo D:/alter/quartusII/newprojec/seqdet2/simulation/activehdl/ simulation " "Info: Generated files \"seqdet2.vo\" and \"seqdet2_v.sdo\" in directory \"D:/alter/quartusII/newprojec/seqdet2/simulation/activehdl/\" for EDA simulation tool" {  } {  } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0}
{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "seqdet2.vo seqdet2_v.sdo D:/alter/quartusII/newprojec/seqdet2/timing/primetime/ timing analysis " "Info: Generated files \"seqdet2.vo\" and \"seqdet2_v.sdo\" in directory \"D:/alter/quartusII/newprojec/seqdet2/timing/primetime/\" for EDA timing analysis tool" {  } {  } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0}
{ "Info" "IPTO_FILE_GENERATED_MSG" "PrimeTime Tcl script file D:/alter/quartusII/newprojec/seqdet2/timing/primetime/seqdet2_pt_v.tcl " "Info: Generated PrimeTime Tcl script file D:/alter/quartusII/newprojec/seqdet2/timing/primetime/seqdet2_pt_v.tcl" {  } {  } 0 0 "Generated %1!s! %2!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 22 16:39:17 2009 " "Info: Processing ended: Sun Feb 22 16:39:17 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}