seqdet2.vo

状态机实现序列检测VerilogHDL及其仿真

stratix_lcell \Selector4~40_I (
// Equation(s):
// \Selector4~40  = \state.L  # \state.K  # \state.J  # !\state.IDLE 

	.clk(gnd),
	.dataa(\state.IDLE ),
	.datab(\state.L ),
	.datac(\state.K ),
	.datad(\state.J ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Selector4~40 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Selector4~40_I .lut_mask = "FFFD";
defparam \Selector4~40_I .operation_mode = "normal";
defparam \Selector4~40_I .output_mode = "comb_only";
defparam \Selector4~40_I .register_cascade_mode = "off";
defparam \Selector4~40_I .sum_lutc_input = "datac";
defparam \Selector4~40_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X1_Y1_N4
stratix_lcell \state.A~I (
// Equation(s):
// \state.A  = DFFEAS(\x~combout  & (\state.D  # \state.E  # \Selector4~40 ), GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(\x~combout ),
	.datab(\state.D ),
	.datac(\state.E ),
	.datad(\Selector4~40 ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.A ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.A~I .lut_mask = "AAA8";
defparam \state.A~I .operation_mode = "normal";
defparam \state.A~I .output_mode = "reg_only";
defparam \state.A~I .register_cascade_mode = "off";
defparam \state.A~I .sum_lutc_input = "datac";
defparam \state.A~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X1_Y1_N2
stratix_lcell \state.B~I (
// Equation(s):
// \state.B  = DFFEAS(\x~combout  & (\state.A  # \state.G  # \state.I ), GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(\state.A ),
	.datab(\x~combout ),
	.datac(\state.G ),
	.datad(\state.I ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.B ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.B~I .lut_mask = "CCC8";
defparam \state.B~I .operation_mode = "normal";
defparam \state.B~I .output_mode = "reg_only";
defparam \state.B~I .register_cascade_mode = "off";
defparam \state.B~I .sum_lutc_input = "datac";
defparam \state.B~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X2_Y1_N6
stratix_lcell \state.C~I (
// Equation(s):
// \state.C  = DFFEAS(\x~combout  & (\state.C  # \state.B ), GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(\x~combout ),
	.datab(\state.C ),
	.datac(vcc),
	.datad(\state.B ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.C ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.C~I .lut_mask = "AA88";
defparam \state.C~I .operation_mode = "normal";
defparam \state.C~I .output_mode = "reg_only";
defparam \state.C~I .register_cascade_mode = "off";
defparam \state.C~I .sum_lutc_input = "datac";
defparam \state.C~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X2_Y1_N0
stratix_lcell \state.D~I (
// Equation(s):
// \state.D  = DFFEAS(!\x~combout  & (\state.C ), GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(\x~combout ),
	.datab(vcc),
	.datac(vcc),
	.datad(\state.C ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.D ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.D~I .lut_mask = "5500";
defparam \state.D~I .operation_mode = "normal";
defparam \state.D~I .output_mode = "reg_only";
defparam \state.D~I .register_cascade_mode = "off";
defparam \state.D~I .sum_lutc_input = "datac";
defparam \state.D~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X2_Y1_N7
stratix_lcell \state.E~I (
// Equation(s):
// \state.E  = DFFEAS(\state.D  & (!\x~combout ), GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\state.D ),
	.datac(vcc),
	.datad(\x~combout ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.E ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.E~I .lut_mask = "00CC";
defparam \state.E~I .operation_mode = "normal";
defparam \state.E~I .output_mode = "reg_only";
defparam \state.E~I .register_cascade_mode = "off";
defparam \state.E~I .sum_lutc_input = "datac";
defparam \state.E~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X2_Y1_N5
stratix_lcell \state.F~I (
// Equation(s):
// \state.F  = DFFEAS(\state.E  & !\x~combout , GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\state.E ),
	.datad(\x~combout ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.F ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.F~I .lut_mask = "00F0";
defparam \state.F~I .operation_mode = "normal";
defparam \state.F~I .output_mode = "reg_only";
defparam \state.F~I .register_cascade_mode = "off";
defparam \state.F~I .sum_lutc_input = "datac";
defparam \state.F~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X1_Y1_N8
stratix_lcell \state.G~I (
// Equation(s):
// \state.G  = DFFEAS(\x~combout  & (\state.F ), GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\x~combout ),
	.datac(vcc),
	.datad(\state.F ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.G ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.G~I .lut_mask = "CC00";
defparam \state.G~I .operation_mode = "normal";
defparam \state.G~I .output_mode = "reg_only";
defparam \state.G~I .register_cascade_mode = "off";
defparam \state.G~I .sum_lutc_input = "datac";
defparam \state.G~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X1_Y1_N0
stratix_lcell \state.H~I (
// Equation(s):
// \state.H  = DFFEAS(\state.G  & !\x~combout , GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\state.G ),
	.datad(\x~combout ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.H ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.H~I .lut_mask = "00F0";
defparam \state.H~I .operation_mode = "normal";
defparam \state.H~I .output_mode = "reg_only";
defparam \state.H~I .register_cascade_mode = "off";
defparam \state.H~I .sum_lutc_input = "datac";
defparam \state.H~I .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_U19
stratix_io \z~I (
	.datain(\z~0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(z),
	.dqsundelayedout());
// synopsys translate_off
defparam \z~I .ddio_mode = "none";
defparam \z~I .input_async_reset = "none";
defparam \z~I .input_power_up = "low";
defparam \z~I .input_register_mode = "none";
defparam \z~I .input_sync_reset = "none";
defparam \z~I .oe_async_reset = "none";
defparam \z~I .oe_power_up = "low";
defparam \z~I .oe_register_mode = "none";
defparam \z~I .oe_sync_reset = "none";
defparam \z~I .operation_mode = "output";
defparam \z~I .output_async_reset = "none";
defparam \z~I .output_power_up = "low";
defparam \z~I .output_register_mode = "none";
defparam \z~I .output_sync_reset = "none";
// synopsys translate_on

endmodule