baud.vhd

来自「FPGA的串口模块」· VHDL 代码 · 共 22 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity baud is
    Port (clk,resetb:in std_logic;
	     bclk:out std_logic);
end baud;
architecture Behavioral of baud is
begin
process(clk,resetb)
variable cnt:integer;
begin
  if resetb='1' then cnt:=0; bclk<='0';                           --复位
  elsif rising_edge(clk) then
     if cnt>=129 then cnt:=0; bclk<='1';                        --设置分频系数
	 else cnt:=cnt+1; bclk<='0';
	 end if;
  end if;
end process;
end Behavioral;