uart.tan.summary

FPGA的串口模块

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 12.200 ns
From           : txdbuf_in[0]
To             : transfer:inst2|txds
From Clock     : --
To Clock       : clk32mhz
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.100 ns
From           : reciever:inst1|r_ready
To             : rec_ready
From Clock     : clk32mhz
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.100 ns
From           : rxd
To             : reciever:inst1|state.r_center
From Clock     : --
To Clock       : clk32mhz
Failed Paths   : 0

Type           : Clock Setup: 'clk32mhz'
Slack          : N/A
Required Time  : None
Actual Time    : 38.61 MHz ( period = 25.900 ns )
From           : reciever:inst1|\pro2:rcnt[1]
To             : reciever:inst1|\pro2:rcnt[30]
From Clock     : clk32mhz
To Clock       : clk32mhz
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------