uart.tan.qmsg

FPGA的串口模块

{ "Info" "ITDB_TSU_RESULT" "transfer:inst2\|txds txdbuf_in\[1\] clk32mhz 12.200 ns register " "Info: tsu for register \"transfer:inst2\|txds\" (data pin = \"txdbuf_in\[1\]\", clock pin = \"clk32mhz\") is 12.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.700 ns + Longest pin register " "Info: + Longest pin to register delay is 20.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns txdbuf_in\[1\] 1 PIN PIN_42 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'txdbuf_in\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { txdbuf_in[1] } "NODE_NAME" } } { "uart.bdf" "" { Schematic "D:/altera/example/uart/uart.bdf" { { 256 -72 96 272 "txdbuf_in\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.300 ns) 9.500 ns transfer:inst2\|Mux0~15 2 COMB LC5_F16 1 " "Info: 2: + IC(3.700 ns) + CELL(2.300 ns) = 9.500 ns; Loc. = LC5_F16; Fanout = 1; COMB Node = 'transfer:inst2\|Mux0~15'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { txdbuf_in[1] transfer:inst2|Mux0~15 } "NODE_NAME" } } { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 12.400 ns transfer:inst2\|Mux0~16 3 COMB LC6_F16 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 12.400 ns; Loc. = LC6_F16; Fanout = 1; COMB Node = 'transfer:inst2\|Mux0~16'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { transfer:inst2|Mux0~15 transfer:inst2|Mux0~16 } "NODE_NAME" } } { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 15.300 ns transfer:inst2\|Selector10~296 4 COMB LC2_F16 1 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 15.300 ns; Loc. = LC2_F16; Fanout = 1; COMB Node = 'transfer:inst2\|Selector10~296'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { transfer:inst2|Mux0~16 transfer:inst2|Selector10~296 } "NODE_NAME" } } { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(1.700 ns) 20.700 ns transfer:inst2\|txds 5 REG LC3_B21 2 " "Info: 5: + IC(3.700 ns) + CELL(1.700 ns) = 20.700 ns; Loc. = LC3_B21; Fanout = 2; REG Node = 'transfer:inst2\|txds'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.400 ns" { transfer:inst2|Selector10~296 transfer:inst2|txds } "NODE_NAME" } } { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.100 ns ( 58.45 % ) " "Info: Total cell delay = 12.100 ns ( 58.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.600 ns ( 41.55 % ) " "Info: Total interconnect delay = 8.600 ns ( 41.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "20.700 ns" { txdbuf_in[1] transfer:inst2|Mux0~15 transfer:inst2|Mux0~16 transfer:inst2|Selector10~296 transfer:inst2|txds } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "20.700 ns" { txdbuf_in[1] {} txdbuf_in[1]~out {} transfer:inst2|Mux0~15 {} transfer:inst2|Mux0~16 {} transfer:inst2|Selector10~296 {} transfer:inst2|txds {} } { 0.000ns 0.000ns 3.700ns 0.600ns 0.600ns 3.700ns } { 0.000ns 3.500ns 2.300ns 2.300ns 2.300ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk32mhz destination 11.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk32mhz\" to destination register is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk32mhz 1 CLK PIN_55 32 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 32; CLK Node = 'clk32mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk32mhz } "NODE_NAME" } } { "uart.bdf" "" { Schematic "D:/altera/example/uart/uart.bdf" { { 72 -32 136 88 "clk32mhz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns baud:inst\|bclk 2 REG LC1_D13 101 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_D13; Fanout = 101; REG Node = 'baud:inst\|bclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clk32mhz baud:inst|bclk } "NODE_NAME" } } { "baud.vhd" "" { Text "D:/altera/example/uart/baud.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.000 ns transfer:inst2\|txds 3 REG LC3_B21 2 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 11.000 ns; Loc. = LC3_B21; Fanout = 2; REG Node = 'transfer:inst2\|txds'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { baud:inst|bclk transfer:inst2|txds } "NODE_NAME" } } { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 35.45 % ) " "Info: Total cell delay = 3.900 ns ( 35.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns ( 64.55 % ) " "Info: Total interconnect delay = 7.100 ns ( 64.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.000 ns" { clk32mhz baud:inst|bclk transfer:inst2|txds } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.000 ns" { clk32mhz {} clk32mhz~out {} baud:inst|bclk {} transfer:inst2|txds {} } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "20.700 ns" { txdbuf_in[1] transfer:inst2|Mux0~15 transfer:inst2|Mux0~16 transfer:inst2|Selector10~296 transfer:inst2|txds } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "20.700 ns" { txdbuf_in[1] {} txdbuf_in[1]~out {} transfer:inst2|Mux0~15 {} transfer:inst2|Mux0~16 {} transfer:inst2|Selector10~296 {} transfer:inst2|txds {} } { 0.000ns 0.000ns 3.700ns 0.600ns 0.600ns 3.700ns } { 0.000ns 3.500ns 2.300ns 2.300ns 2.300ns 1.700ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.000 ns" { clk32mhz baud:inst|bclk transfer:inst2|txds } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.000 ns" { clk32mhz {} clk32mhz~out {} baud:inst|bclk {} transfer:inst2|txds {} } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk32mhz rec_ready reciever:inst1\|r_ready 21.100 ns register " "Info: tco from clock \"clk32mhz\" to destination pin \"rec_ready\" through register \"reciever:inst1\|r_ready\" is 21.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk32mhz source 11.000 ns + Longest register " "Info: + Longest clock path from clock \"clk32mhz\" to source register is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk32mhz 1 CLK PIN_55 32 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 32; CLK Node = 'clk32mhz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk32mhz } "NODE_NAME" } } { "uart.bdf" "" { Schematic "D:/altera/example/uart/uart.bdf" { { 72 -32 136 88 "clk32mhz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns baud:inst\|bclk 2 REG LC1_D13 101 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_D13; Fanout = 101; REG Node = 'baud:inst\|bclk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clk32mhz baud:inst|bclk } "NODE_NAME" } } { "baud.vhd" "" { Text "D:/altera/example/uart/baud.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.000 ns reciever:inst1\|r_ready 3 REG LC4_E18 2 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 11.000 ns; Loc. = LC4_E18; Fanout = 2; REG Node = 'reciever:inst1\|r_ready'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { baud:inst|bclk reciever:inst1|r_ready } "NODE_NAME" } } { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 35.45 % ) " "Info: Total cell delay = 3.900 ns ( 35.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns ( 64.55 % ) " "Info: Total interconnect delay = 7.100 ns ( 64.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.000 ns" { clk32mhz baud:inst|bclk reciever:inst1|r_ready } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.000 ns" { clk32mhz {} clk32mhz~out {} baud:inst|bclk {} reciever:inst1|r_ready {} } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register pin " "Info: + Longest register to pin delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reciever:inst1\|r_ready 1 REG LC4_E18 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_E18; Fanout = 2; REG Node = 'reciever:inst1\|r_ready'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reciever:inst1|r_ready } "NODE_NAME" } } { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(5.100 ns) 9.000 ns rec_ready 2 PIN PIN_101 0 " "Info: 2: + IC(3.900 ns) + CELL(5.100 ns) = 9.000 ns; Loc. = PIN_101; Fanout = 0; PIN Node = 'rec_ready'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { reciever:inst1|r_ready rec_ready } "NODE_NAME" } } { "uart.bdf" "" { Schematic "D:/altera/example/uart/uart.bdf" { { 72 512 688 88 "rec_ready" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 56.67 % ) " "Info: Total cell delay = 5.100 ns ( 56.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns ( 43.33 % ) " "Info: Total interconnect delay = 3.900 ns ( 43.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quart