uart.sim.rpt

FPGA的串口模块

; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;       3.33 % ;
; Total nodes checked                                 ; 337          ;
; Total output ports checked                          ; 390          ;
; Total output ports with complete 1/0-value coverage ; 13           ;
; Total output ports with no 1/0-value coverage       ; 375          ;
; Total output ports with no 1-value coverage         ; 376          ;
; Total output ports with no 0-value coverage         ; 376          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                         ;
+--------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                            ; Output Port Name                                                                          ; Output Port Type ;
+--------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT ; cout             ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[5]                 ; data_out0        ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT ; cout             ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[4]                 ; data_out0        ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT ; cout             ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3]                 ; data_out0        ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT ; cout             ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2]                 ; data_out0        ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT ; cout             ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1]                 ; data_out0        ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ; cout             ;
; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; |uart|baud:inst|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT ; cout             ;
; |uart|clk32mhz                                                                       ; |uart|clk32mhz~corein                                                                     ; dataout          ;
+--------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                  ;
+-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                 ; Output Port Name                                                                           ; Output Port Type ;
+-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; |uart|transfer:inst2|txds                                                                 ; |uart|transfer:inst2|txds                                                                  ; data_out0        ;
; |uart|reciever:inst1|rbuf[7]                                                              ; |uart|reciever:inst1|rbuf[7]                                                               ; data_out0        ;
; |uart|reciever:inst1|rbuf[6]                                                              ; |uart|reciever:inst1|rbuf[6]                                                               ; data_out0        ;
; |uart|reciever:inst1|rbuf[5]                                                              ; |uart|reciever:inst1|rbuf[5]                                                               ; data_out0        ;
; |uart|reciever:inst1|rbuf[4]                                                              ; |uart|reciever:inst1|rbuf[4]                                                               ; data_out0        ;
; |uart|reciever:inst1|rbuf[3]                                                              ; |uart|reciever:inst1|rbuf[3]                                                               ; data_out0        ;
; |uart|reciever:inst1|rbuf[2]                                                              ; |uart|reciever:inst1|rbuf[2]                                                               ; data_out0        ;
; |uart|reciever:inst1|rbuf[1]                                                              ; |uart|reciever:inst1|rbuf[1]                                                               ; data_out0        ;
; |uart|reciever:inst1|rbuf[0]                                                              ; |uart|reciever:inst1|rbuf[0]                                                               ; data_out0        ;
; |uart|reciever:inst1|state.r_stop                                                         ; |uart|reciever:inst1|state.r_stop                                                          ; data_out0        ;
; |uart|reciever:inst1|state.r_start                                                        ; |uart|reciever:inst1|state.r_start                                                         ; data_out0        ;
; |uart|baud:inst|bclk                                                                      ; |uart|baud:inst|bclk                                                                       ; data_out0        ;
; |uart|transfer:inst2|state.x_stop                                                         ; |uart|transfer:inst2|state.x_stop                                                          ; data_out0        ;
; |uart|transfer:inst2|state.x_wait                                                         ; |uart|transfer:inst2|state.x_wait                                                          ; data_out0        ;
; |uart|transfer:inst2|state.x_idle                                                         ; |uart|transfer:inst2|state.x_idle                                                          ; data_out0        ;
; |uart|transfer:inst2|Selector10~285                                                       ; |uart|transfer:inst2|Selector10~285                                                        ; data_out0        ;
; |uart|transfer:inst2|state.x_start                                                        ; |uart|transfer:inst2|state.x_start                                                         ; data_out0        ;
; |uart|transfer:inst2|xcnt16[2]                                                            ; |uart|transfer:inst2|xcnt16[2]                                                             ; data_out0        ;
; |uart|transfer:inst2|xcnt16[1]                                                            ; |uart|transfer:inst2|xcnt16[1]                                                             ; data_out0        ;
; |uart|transfer:inst2|LessThan0~77                                                         ; |uart|transfer:inst2|LessThan0~77                                                          ; data_out0        ;
; |uart|transfer:inst2|Selector10~286                                                       ; |uart|transfer:inst2|Selector10~286                                                        ; data_out0        ;
; |uart|transfer:inst2|state.x_shift                                                        ; |uart|transfer:inst2|state.x_shift                                                         ; data_out0        ;
; |uart|transfer:inst2|xbitcnt[0]                                                           ; |uart|transfer:inst2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[0]        ; cout             ;
; |uart|transfer:inst2|xbitcnt[1]                                                           ; |uart|transfer:inst2|xbitcnt[1]                                                            ; data_out0        ;
; |uart|transfer:inst2|Mux0~13                                                              ; |uart|transfer:inst2|Mux0~13                                                               ; data_out0        ;
; |uart|transfer:inst2|Mux0~14                                                              ; |uart|transfer:inst2|Mux0~14                                                               ; data_out0        ;