fmul.fnsim.qmsg

本程序是11位带符号位的乘法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Web Edition " "Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 21 20:12:32 2009 " "Info: Processing started: Sat Feb 21 20:12:32 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fmul -c fmul --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fmul -c fmul --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mul11.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mul11.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fmul-Behavioral " "Info: Found design unit 1: fmul-Behavioral" {  } { { "mul11.vhd" "" { Text "C:/altera/80/quartus/Multi11/mul11.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fmul " "Info: Found entity 1: fmul" {  } { { "mul11.vhd" "" { Text "C:/altera/80/quartus/Multi11/mul11.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fmul " "Info: Elaborating entity \"fmul\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult0 lpm_mult " "Info: Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult0\"" {  } { { "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "Mult0" { Text "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 687 -1 0 } }  } 0 0 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"lpm_mult:Mult0\"" {  } { { "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 687 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult0 " "Info: Instantiated megafunction \"lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Info: Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 4 " "Info: Parameter \"LPM_WIDTHB\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 8 " "Info: Parameter \"LPM_WIDTHP\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 8 " "Info: Parameter \"LPM_WIDTHR\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Info: Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Info: Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Info: Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Info: Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEDICATED_MULTIPLIER_CIRCUITRY AUTO " "Info: Parameter \"DEDICATED_MULTIPLIER_CIRCUITRY\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 687 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_lq01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_lq01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_lq01 " "Info: Found entity 1: mult_lq01" {  } { { "db/mult_lq01.tdf" "" { Text "C:/altera/80/quartus/Multi11/db/mult_lq01.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Warning: Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Warning: Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "lpm_mult:Mult0\|mult_lq01:auto_generated\|le5a\[4\] " "Warning (14320): Synthesized away node \"lpm_mult:Mult0\|mult_lq01:auto_generated\|le5a\[4\]\"" {  } { { "db/mult_lq01.tdf" "" { Text "C:/altera/80/quartus/Multi11/db/mult_lq01.tdf" 42 6 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 687 -1 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 0}  } {  } 0 0 "Synthesized away the following node(s):" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 3 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "175 " "Info: Peak virtual memory: 175 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 21 20:12:34 2009 " "Info: Processing ended: Sat Feb 21 20:12:34 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}