prev_cmp_fmul.map.qmsg

本程序是11位带符号位的乘法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Web Edition " "Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 21 20:08:35 2009 " "Info: Processing started: Sat Feb 21 20:08:35 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fmul -c fmul " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fmul -c fmul" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mul11.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mul11.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fmul-Behavioral " "Info: Found design unit 1: fmul-Behavioral" {  } { { "mul11.vhd" "" { Text "C:/altera/80/quartus/Multi11/mul11.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fmul " "Info: Found entity 1: fmul" {  } { { "mul11.vhd" "" { Text "C:/altera/80/quartus/Multi11/mul11.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fmul " "Info: Elaborating entity \"fmul\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Error" "EVRFX_VHDL_ERROR_INDEX_VALUE_IS_OUTSIDE_ARRAY_RANGE" "10 7 downto 0 tempm mul11.vhd(118) " "Error (10385): VHDL error at mul11.vhd(118): index value 10 is outside the range (7 downto 0) of object \"tempm\"" {  } { { "mul11.vhd" "" { Text "C:/altera/80/quartus/Multi11/mul11.vhd" 118 0 0 } }  } 0 10385 "VHDL error at %4!s!: index value %1!s! is outside the range (%2!s!) of object \"%3!s!\"" 0 0 "" 0 0}
{ "Error" "EVRFX_VHDL_OPERATOR_CALL_FAILED" "\"=\" mul11.vhd(118) " "Error (10658): VHDL Operator error at mul11.vhd(118): failed to evaluate call to operator \"\"=\"\"" {  } { { "mul11.vhd" "" { Text "C:/altera/80/quartus/Multi11/mul11.vhd" 118 0 0 } }  } 0 10658 "VHDL Operator error at %2!s!: failed to evaluate call to operator \"%1!s!\"" 0 0 "" 0 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "172 " "Error: Peak virtual memory: 172 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Sat Feb 21 20:08:37 2009 " "Error: Processing ended: Sat Feb 21 20:08:37 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Error: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}