fmul.sim.rpt

本程序是11位带符号位的乘法器

; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~183     ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~183        ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~184     ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~184        ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~185     ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~185        ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~186     ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~186        ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs1a[1]   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs1a[1]      ; sout             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs1a[0]   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs1a[0]~COUT ; cout             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs1a[0]   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs1a[0]      ; sout             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs2a[1]   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs2a[1]      ; sout             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs2a[0]   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs2a[0]~COUT ; cout             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs2a[0]   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|cs2a[0]      ; sout             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|le5a[2]   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|le5a[2]      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|le5a[1]   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|le5a[1]      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|le5a[0]   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|le5a[0]      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|sft12a[0] ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|sft12a[0]    ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|sft8a[0]  ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|sft8a[0]     ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~40   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~40      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~41   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~41      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~42   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~42      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~43   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~43      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~44   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~44      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~45   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~45      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~46   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~46      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~47   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~47      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~48   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~48      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~49   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~49      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~50   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~50      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~51   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~51      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~52   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~52      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~53   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~53      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~54   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~54      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~55   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~55      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~56   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~56      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~57   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~57      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~58   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~58      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~59   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_1~59      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~55   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~55      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~56   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~56      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~57   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~57      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~58   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~58      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~59   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~59      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~60   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~60      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~61   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~61      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~62   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~62      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~63   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~63      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~64   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~64      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~65   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~65      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~66   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~66      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~67   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~67      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~68   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~68      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~69   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~69      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~70   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~70      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~71   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~71      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~72   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~72      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~73   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~73      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~74   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~74      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~75   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~75      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~76   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~76      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~77   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~77      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~78   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~78      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~79   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~79      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~80   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~80      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~81   ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|op_3~81      ; out0             ;
+---------------------------------------------------------+------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                     ;
+-----------------------------------------------------+-----------------------------------------------------+------------------+
; Node Name                                           ; Output Port Name                                    ; Output Port Type ;
+-----------------------------------------------------+-----------------------------------------------------+------------------+
; |fmul|process0~0                                    ; |fmul|process0~0                                    ; out0             ;
; |fmul|process0~1                                    ; |fmul|process0~1                                    ; out0             ;
; |fmul|Equal0~9                                      ; |fmul|Equal0~9                                      ; out0             ;
; |fmul|Equal3~9                                      ; |fmul|Equal3~9                                      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~167 ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~167 ; out0             ;
+-----------------------------------------------------+-----------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                     ;
+-----------------------------------------------------+-----------------------------------------------------+------------------+
; Node Name                                           ; Output Port Name                                    ; Output Port Type ;
+-----------------------------------------------------+-----------------------------------------------------+------------------+
; |fmul|process0~0                                    ; |fmul|process0~0                                    ; out0             ;
; |fmul|process0~1                                    ; |fmul|process0~1                                    ; out0             ;
; |fmul|Equal0~9                                      ; |fmul|Equal0~9                                      ; out0             ;
; |fmul|Equal3~9                                      ; |fmul|Equal3~9                                      ; out0             ;
; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~167 ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated|_~167 ; out0             ;
+-----------------------------------------------------+-----------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Sat Feb 21 21:39:03 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off fmul -c fmul
Info: Using vector source file "C:/altera/80/quartus/Multi11/fmul.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      98.45 %
Info: Number of transitions in simulation is 62848
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 109 megabytes
    Info: Processing ended: Sat Feb 21 21:39:04 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01