📄 fmul.map.rpt
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; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 59 ;
; -- arithmetic mode ; 31 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 34 ;
; Maximum fan-out node ; b4[1] ;
; Maximum fan-out ; 14 ;
; Total fan-out ; 278 ;
; Average fan-out ; 2.24 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------+--------------+
; |fmul ; 90 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 34 ; 0 ; |fmul ; work ;
; |lpm_mult:Mult0| ; 30 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |fmul|lpm_mult:Mult0 ; work ;
; |mult_lq01:auto_generated| ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |fmul|lpm_mult:Mult0|mult_lq01:auto_generated ; work ;
+----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1 ; 3 bits ; 9 LEs ; 3 LEs ; 6 LEs ; No ; |fmul|tempm[7] ;
; 7:1 ; 6 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |fmul|e~41 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0 ;
+------------------------------------------------+------------+---------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------------------+------------+---------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTHA ; 4 ; Untyped ;
; LPM_WIDTHB ; 4 ; Untyped ;
; LPM_WIDTHP ; 8 ; Untyped ;
; LPM_WIDTHR ; 8 ; Untyped ;
; LPM_WIDTHS ; 1 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LATENCY ; 0 ; Untyped ;
; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
; USE_EAB ; OFF ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
; CBXI_PARAMETER ; mult_lq01 ; Untyped ;
; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
+------------------------------------------------+------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance ;
+---------------------------------------+----------------+
; Name ; Value ;
+---------------------------------------+----------------+
; Number of entity instances ; 1 ;
; Entity Instance ; lpm_mult:Mult0 ;
; -- LPM_WIDTHA ; 4 ;
; -- LPM_WIDTHB ; 4 ;
; -- LPM_WIDTHP ; 8 ;
; -- LPM_REPRESENTATION ; UNSIGNED ;
; -- INPUT_A_IS_CONSTANT ; NO ;
; -- INPUT_B_IS_CONSTANT ; NO ;
; -- USE_EAB ; OFF ;
; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;
; -- INPUT_A_FIXED_VALUE ; Bx ;
; -- INPUT_B_FIXED_VALUE ; Bx ;
+---------------------------------------+----------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
Info: Processing started: Sat Feb 21 20:09:04 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fmul -c fmul
Info: Found 2 design units, including 1 entities, in source file mul11.vhd
Info: Found design unit 1: fmul-Behavioral
Info: Found entity 1: fmul
Info: Elaborating entity "fmul" for the top level hierarchy
Info: Inferred 1 megafunctions from design logic
Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Mult0"
Info: Elaborated megafunction instantiation "lpm_mult:Mult0"
Info: Instantiated megafunction "lpm_mult:Mult0" with the following parameter:
Info: Parameter "LPM_WIDTHA" = "4"
Info: Parameter "LPM_WIDTHB" = "4"
Info: Parameter "LPM_WIDTHP" = "8"
Info: Parameter "LPM_WIDTHR" = "8"
Info: Parameter "LPM_WIDTHS" = "1"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"
Info: Parameter "INPUT_B_IS_CONSTANT" = "NO"
Info: Parameter "MAXIMIZE_SPEED" = "5"
Info: Parameter "DEDICATED_MULTIPLIER_CIRCUITRY" = "AUTO"
Info: Found 1 design units, including 1 entities, in source file db/mult_lq01.tdf
Info: Found entity 1: mult_lq01
Warning: Synthesized away the following node(s):
Warning: Synthesized away the following LCELL buffer node(s):
Warning (14320): Synthesized away node "lpm_mult:Mult0|mult_lq01:auto_generated|le5a[4]"
Info: Ignored 43 buffer(s)
Info: Ignored 2 CARRY_SUM buffer(s)
Info: Ignored 41 SOFT buffer(s)
Info: Found the following redundant logic cells in design
Info (17048): Logic cell "lpm_mult:Mult0|mult_lq01:auto_generated|le5a[0]"
Info (17048): Logic cell "lpm_mult:Mult0|mult_lq01:auto_generated|le3a[5]"
Info (17048): Logic cell "lpm_mult:Mult0|mult_lq01:auto_generated|le5a[3]"
Info (17048): Logic cell "lpm_mult:Mult0|mult_lq01:auto_generated|le5a[2]"
Info (17048): Logic cell "lpm_mult:Mult0|mult_lq01:auto_generated|le5a[1]"
Info: Implemented 124 device resources after synthesis - the final resource count might be different
Info: Implemented 22 input pins
Info: Implemented 12 output pins
Info: Implemented 90 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 175 megabytes
Info: Processing ended: Sat Feb 21 20:09:07 2009
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03
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