prev_cmp_plltest.map.qmsg

Altera Quartus to Pll Source

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 08 16:44:21 2009 " "Info: Processing started: Thu Jan 08 16:44:21 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PLLTEST -c PLLTEST " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PLLTEST -c PLLTEST" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PLLTEST.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file PLLTEST.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 PLLTEST " "Info: Found entity 1: PLLTEST" {  } { { "PLLTEST.bdf" "" { Schematic "D:/quartus_work/PLLTEST/PLLTEST.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "PLLTEST " "Info: Elaborating entity \"PLLTEST\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "VCC inst3 " "Warning: Primitive \"VCC\" of instance \"inst3\" not used" {  } { { "PLLTEST.bdf" "" { Schematic "D:/quartus_work/PLLTEST/PLLTEST.bdf" { { 136 536 568 152 "inst3" "" } } } }  } 0 0 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 freqdiv " "Info: Found entity 1: freqdiv" {  } { { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "freqdiv freqdiv:inst8 " "Info: Elaborating entity \"freqdiv\" for hierarchy \"freqdiv:inst8\"" {  } { { "PLLTEST.bdf" "inst8" { Schematic "D:/quartus_work/PLLTEST/PLLTEST.bdf" { { 112 632 752 224 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "freqdiv " "Warning: Processing legacy GDF or BDF entity \"freqdiv\" with Max+Plus II bus and instance naming rules" {  } { { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Warning" "WGDFX_MIXED_DESIGN_FILE_NAMING" "" "Warning: The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s)." {  } { { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { } } }  } 0 0 "The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s)." 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "freqdiv:inst8 " "Info: Elaborated megafunction instantiation \"freqdiv:inst8\"" {  } { { "PLLTEST.bdf" "" { Schematic "D:/quartus_work/PLLTEST/PLLTEST.bdf" { { 112 632 752 224 "inst8" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "PLLT.vhd 2 1 " "Warning: Using design file PLLT.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pllt-SYN " "Info: Found design unit 1: pllt-SYN" {  } { { "PLLT.vhd" "" { Text "D:/quartus_work/PLLTEST/PLLT.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 PLLT " "Info: Found entity 1: PLLT" {  } { { "PLLT.vhd" "" { Text "D:/quartus_work/PLLTEST/PLLT.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLLT PLLT:inst " "Info: Elaborating entity \"PLLT\" for hierarchy \"PLLT:inst\"" {  } { { "PLLTEST.bdf" "inst" { Schematic "D:/quartus_work/PLLTEST/PLLTEST.bdf" { { 136 272 536 296 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 476 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll PLLT:inst\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"PLLT:inst\|altpll:altpll_component\"" {  } { { "PLLT.vhd" "altpll_component" { Text "D:/quartus_work/PLLTEST/PLLT.vhd" 139 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "PLLT:inst\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"PLLT:inst\|altpll:altpll_component\"" {  } { { "PLLT.vhd" "" { Text "D:/quartus_work/PLLTEST/PLLT.vhd" 139 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "10 " "Info: Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Info: Implemented 4 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "166 " "Info: Allocated 166 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 08 16:44:27 2009 " "Info: Processing ended: Thu Jan 08 16:44:27 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}