plltest.hier_info

Altera Quartus to Pll Source

|PLLTEST
C1212 <= freqdiv:inst8.DV16
clk => PLLT:inst.inclk0
C1213 <= freqdiv:inst8.DV8
C1214 <= freqdiv:inst8.DV4
C1215 <= freqdiv:inst8.DV2


|PLLTEST|freqdiv:inst8
DV16 <= 24.DB_MAX_OUTPUT_PORT_TYPE
CLR => 20.IN0
G => 29.IN0
G => 21~0.IN0
CLK => 21.CLK
CLK => 22.CLK
CLK => 23.CLK
CLK => 24.CLK
DV8 <= 23.DB_MAX_OUTPUT_PORT_TYPE
DV4 <= 22.DB_MAX_OUTPUT_PORT_TYPE
DV2 <= 21.DB_MAX_OUTPUT_PORT_TYPE


|PLLTEST|PLLT:inst
areset => altpll:altpll_component.areset
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]
locked <= altpll:altpll_component.locked


|PLLTEST|PLLT:inst|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= pll.LOCKED
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>