prev_cmp_plltest.tan.qmsg

Altera Quartus to Pll Source

{ "Info" "ITDB_FULL_TCO_RESULT" "clk C1215 freqdiv:inst8\|21 4.675 ns register " "Info: tco from clock \"clk\" to destination pin \"C1215\" through register \"freqdiv:inst8\|21\" is 4.675 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk PLLT:inst\|altpll:altpll_component\|_clk0 -2.388 ns + " "Info: + Offset between input clock \"clk\" and output clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" is -2.388 ns" {  } { { "PLLTEST.bdf" "" { Schematic "D:/quartus_work/PLLTEST/PLLTEST.bdf" { { 192 32 200 208 "clk" "" } } } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLLT:inst\|altpll:altpll_component\|_clk0 source 2.503 ns + Longest register " "Info: + Longest clock path from clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" to source register is 2.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLLT:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLLT:inst\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLLT:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns PLLT:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'PLLT:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.503 ns freqdiv:inst8\|21 3 REG LCFF_X1_Y2_N31 5 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.503 ns; Loc. = LCFF_X1_Y2_N31; Fanout = 5; REG Node = 'freqdiv:inst8\|21'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|21 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 16 488 552 96 "21" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 26.61 % ) " "Info: Total cell delay = 0.666 ns ( 26.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.837 ns ( 73.39 % ) " "Info: Total interconnect delay = 1.837 ns ( 73.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|21 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|21 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 16 488 552 96 "21" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.256 ns + Longest register pin " "Info: + Longest register to pin delay is 4.256 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freqdiv:inst8\|21 1 REG LCFF_X1_Y2_N31 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N31; Fanout = 5; REG Node = 'freqdiv:inst8\|21'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { freqdiv:inst8|21 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 16 488 552 96 "21" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.150 ns) + CELL(3.106 ns) 4.256 ns C1215 2 PIN PIN_43 0 " "Info: 2: + IC(1.150 ns) + CELL(3.106 ns) = 4.256 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'C1215'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.256 ns" { freqdiv:inst8|21 C1215 } "NODE_NAME" } } { "PLLTEST.bdf" "" { Schematic "D:/quartus_work/PLLTEST/PLLTEST.bdf" { { 128 800 976 144 "C1215" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.106 ns ( 72.98 % ) " "Info: Total cell delay = 3.106 ns ( 72.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.150 ns ( 27.02 % ) " "Info: Total interconnect delay = 1.150 ns ( 27.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.256 ns" { freqdiv:inst8|21 C1215 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.256 ns" { freqdiv:inst8|21 {} C1215 {} } { 0.000ns 1.150ns } { 0.000ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|21 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|21 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.256 ns" { freqdiv:inst8|21 C1215 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.256 ns" { freqdiv:inst8|21 {} C1215 {} } { 0.000ns 1.150ns } { 0.000ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." {  } {  } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 08 16:44:49 2009 " "Info: Processing ended: Thu Jan 08 16:44:49 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}