prev_cmp_plltest.tan.qmsg

Altera Quartus to Pll Source

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "PLLT:inst\|altpll:altpll_component\|_clk0 register freqdiv:inst8\|22 register freqdiv:inst8\|23 1.003 ns " "Info: Slack time is 1.003 ns for clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" between source register \"freqdiv:inst8\|22\" and destination register \"freqdiv:inst8\|23\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "402.58 MHz " "Info: Fmax is restricted to 402.58 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.235 ns + Largest register register " "Info: + Largest register to register requirement is 2.235 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "2.499 ns + " "Info: + Setup relationship between source and destination is 2.499 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.111 ns " "Info: + Latch edge is 0.111 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLLT:inst\|altpll:altpll_component\|_clk0 2.499 ns -2.388 ns  50 " "Info: Clock period of Destination clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" is 2.499 ns with  offset of -2.388 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.388 ns " "Info: - Launch edge is -2.388 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLLT:inst\|altpll:altpll_component\|_clk0 2.499 ns -2.388 ns  50 " "Info: Clock period of Source clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" is 2.499 ns with  offset of -2.388 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLLT:inst\|altpll:altpll_component\|_clk0 destination 2.503 ns + Shortest register " "Info: + Shortest clock path from clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" to destination register is 2.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLLT:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLLT:inst\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLLT:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns PLLT:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'PLLT:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.503 ns freqdiv:inst8\|23 3 REG LCFF_X1_Y2_N23 3 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.503 ns; Loc. = LCFF_X1_Y2_N23; Fanout = 3; REG Node = 'freqdiv:inst8\|23'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 26.61 % ) " "Info: Total cell delay = 0.666 ns ( 26.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.837 ns ( 73.39 % ) " "Info: Total interconnect delay = 1.837 ns ( 73.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLLT:inst\|altpll:altpll_component\|_clk0 source 2.503 ns - Longest register " "Info: - Longest clock path from clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" to source register is 2.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLLT:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLLT:inst\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLLT:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns PLLT:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'PLLT:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.503 ns freqdiv:inst8\|22 3 REG LCFF_X1_Y2_N13 4 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.503 ns; Loc. = LCFF_X1_Y2_N13; Fanout = 4; REG Node = 'freqdiv:inst8\|22'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|22 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 152 488 552 232 "22" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 26.61 % ) " "Info: Total cell delay = 0.666 ns ( 26.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.837 ns ( 73.39 % ) " "Info: Total interconnect delay = 1.837 ns ( 73.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|22 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|22 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|22 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|22 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 152 488 552 232 "22" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|22 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|22 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.232 ns - Longest register register " "Info: - Longest register to register delay is 1.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freqdiv:inst8\|22 1 REG LCFF_X1_Y2_N13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N13; Fanout = 4; REG Node = 'freqdiv:inst8\|22'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { freqdiv:inst8|22 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 152 488 552 232 "22" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.473 ns) + CELL(0.651 ns) 1.124 ns freqdiv:inst8\|23~22 2 COMB LCCOMB_X1_Y2_N22 1 " "Info: 2: + IC(0.473 ns) + CELL(0.651 ns) = 1.124 ns; Loc. = LCCOMB_X1_Y2_N22; Fanout = 1; COMB Node = 'freqdiv:inst8\|23~22'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.124 ns" { freqdiv:inst8|22 freqdiv:inst8|23~22 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.232 ns freqdiv:inst8\|23 3 REG LCFF_X1_Y2_N23 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.232 ns; Loc. = LCFF_X1_Y2_N23; Fanout = 3; REG Node = 'freqdiv:inst8\|23'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { freqdiv:inst8|23~22 freqdiv:inst8|23 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.759 ns ( 61.61 % ) " "Info: Total cell delay = 0.759 ns ( 61.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.473 ns ( 38.39 % ) " "Info: Total interconnect delay = 0.473 ns ( 38.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.232 ns" { freqdiv:inst8|22 freqdiv:inst8|23~22 freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.232 ns" { freqdiv:inst8|22 {} freqdiv:inst8|23~22 {} freqdiv:inst8|23 {} } { 0.000ns 0.473ns 0.000ns } { 0.000ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|22 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|22 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.232 ns" { freqdiv:inst8|22 freqdiv:inst8|23~22 freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.232 ns" { freqdiv:inst8|22 {} freqdiv:inst8|23~22 {} freqdiv:inst8|23 {} } { 0.000ns 0.473ns 0.000ns } { 0.000ns 0.651ns 0.108ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "PLLT:inst\|altpll:altpll_component\|_clk0 register freqdiv:inst8\|23 register freqdiv:inst8\|23 499 ps " "Info: Minimum slack time is 499 ps for clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" between source register \"freqdiv:inst8\|23\" and destination register \"freqdiv:inst8\|23\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Shortest register register " "Info: + Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freqdiv:inst8\|23 1 REG LCFF_X1_Y2_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N23; Fanout = 3; REG Node = 'freqdiv:inst8\|23'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { freqdiv:inst8|23 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns freqdiv:inst8\|23~22 2 COMB LCCOMB_X1_Y2_N22 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X1_Y2_N22; Fanout = 1; COMB Node = 'freqdiv:inst8\|23~22'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { freqdiv:inst8|23 freqdiv:inst8|23~22 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns freqdiv:inst8\|23 3 REG LCFF_X1_Y2_N23 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X1_Y2_N23; Fanout = 3; REG Node = 'freqdiv:inst8\|23'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { freqdiv:inst8|23~22 freqdiv:inst8|23 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { freqdiv:inst8|23 freqdiv:inst8|23~22 freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { freqdiv:inst8|23 {} freqdiv:inst8|23~22 {} freqdiv:inst8|23 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.002 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.002 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.388 ns " "Info: + Latch edge is -2.388 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLLT:inst\|altpll:altpll_component\|_clk0 2.499 ns -2.388 ns  50 " "Info: Clock period of Destination clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" is 2.499 ns with  offset of -2.388 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.388 ns " "Info: - Launch edge is -2.388 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLLT:inst\|altpll:altpll_component\|_clk0 2.499 ns -2.388 ns  50 " "Info: Clock period of Source clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" is 2.499 ns with  offset of -2.388 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLLT:inst\|altpll:altpll_component\|_clk0 destination 2.503 ns + Longest register " "Info: + Longest clock path from clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" to destination register is 2.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLLT:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLLT:inst\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLLT:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns PLLT:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'PLLT:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.503 ns freqdiv:inst8\|23 3 REG LCFF_X1_Y2_N23 3 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.503 ns; Loc. = LCFF_X1_Y2_N23; Fanout = 3; REG Node = 'freqdiv:inst8\|23'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 26.61 % ) " "Info: Total cell delay = 0.666 ns ( 26.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.837 ns ( 73.39 % ) " "Info: Total interconnect delay = 1.837 ns ( 73.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLLT:inst\|altpll:altpll_component\|_clk0 source 2.503 ns - Shortest register " "Info: - Shortest clock path from clock \"PLLT:inst\|altpll:altpll_component\|_clk0\" to source register is 2.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLLT:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLLT:inst\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLLT:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns PLLT:inst\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'PLLT:inst\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.503 ns freqdiv:inst8\|23 3 REG LCFF_X1_Y2_N23 3 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.503 ns; Loc. = LCFF_X1_Y2_N23; Fanout = 3; REG Node = 'freqdiv:inst8\|23'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 26.61 % ) " "Info: Total cell delay = 0.666 ns ( 26.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.837 ns ( 73.39 % ) " "Info: Total interconnect delay = 1.837 ns ( 73.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "freqdiv.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/freqdiv.bdf" { { 280 488 552 360 "23" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { freqdiv:inst8|23 freqdiv:inst8|23~22 freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { freqdiv:inst8|23 {} freqdiv:inst8|23~22 {} freqdiv:inst8|23 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 PLLT:inst|altpll:altpll_component|_clk0~clkctrl freqdiv:inst8|23 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.503 ns" { PLLT:inst|altpll:altpll_component|_clk0 {} PLLT:inst|altpll:altpll_component|_clk0~clkctrl {} freqdiv:inst8|23 {} } { 0.000ns 0.916ns 0.921ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}