plltest.tan.rpt

Altera Quartus to Pll Source

; 0.761 ns      ; freqdiv:inst8|21 ; freqdiv:inst8|22 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.002 ns                   ; 0.763 ns                 ;
; 0.764 ns      ; freqdiv:inst8|21 ; freqdiv:inst8|23 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.002 ns                   ; 0.766 ns                 ;
; 1.186 ns      ; freqdiv:inst8|21 ; freqdiv:inst8|24 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.002 ns                   ; 1.188 ns                 ;
; 1.228 ns      ; freqdiv:inst8|22 ; freqdiv:inst8|24 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.002 ns                   ; 1.230 ns                 ;
; 1.232 ns      ; freqdiv:inst8|22 ; freqdiv:inst8|23 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0.000 ns                   ; 0.002 ns                   ; 1.234 ns                 ;
+---------------+------------------+------------------+-----------------------------------------+-----------------------------------------+----------------------------+----------------------------+--------------------------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From             ; To    ; From Clock ;
+-------+--------------+------------+------------------+-------+------------+
; N/A   ; None         ; 4.649 ns   ; freqdiv:inst8|23 ; C1213 ; clk        ;
; N/A   ; None         ; 4.637 ns   ; freqdiv:inst8|21 ; C1215 ; clk        ;
; N/A   ; None         ; 4.214 ns   ; freqdiv:inst8|24 ; C1212 ; clk        ;
; N/A   ; None         ; 4.200 ns   ; freqdiv:inst8|22 ; C1214 ; clk        ;
+-------+--------------+------------+------------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Jan 08 16:47:25 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PLLTEST -c PLLTEST --timing_analysis_only
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Info: Found timing assignments -- calculating delays
Info: Slack time is 1.359 ns for clock "PLLT:inst|altpll:altpll_component|_clk0" between source register "freqdiv:inst8|22" and destination register "freqdiv:inst8|23"
    Info: Fmax is restricted to 402.58 MHz due to tcl and tch limits
    Info: + Largest register to register requirement is 2.593 ns
        Info: + Setup relationship between source and destination is 2.857 ns
            Info: + Latch edge is 0.469 ns
                Info: Clock period of Destination clock "PLLT:inst|altpll:altpll_component|_clk0" is 2.857 ns with  offset of -2.388 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is -2.388 ns
                Info: Clock period of Source clock "PLLT:inst|altpll:altpll_component|_clk0" is 2.857 ns with  offset of -2.388 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "PLLT:inst|altpll:altpll_component|_clk0" to destination register is 2.494 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLLT:inst|altpll:altpll_component|_clk0'
                Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'PLLT:inst|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(0.912 ns) + CELL(0.666 ns) = 2.494 ns; Loc. = LCFF_X1_Y5_N11; Fanout = 3; REG Node = 'freqdiv:inst8|23'
                Info: Total cell delay = 0.666 ns ( 26.70 % )
                Info: Total interconnect delay = 1.828 ns ( 73.30 % )
            Info: - Longest clock path from clock "PLLT:inst|altpll:altpll_component|_clk0" to source register is 2.494 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLLT:inst|altpll:altpll_component|_clk0'
                Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'PLLT:inst|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(0.912 ns) + CELL(0.666 ns) = 2.494 ns; Loc. = LCFF_X1_Y5_N17; Fanout = 4; REG Node = 'freqdiv:inst8|22'
                Info: Total cell delay = 0.666 ns ( 26.70 % )
                Info: Total interconnect delay = 1.828 ns ( 73.30 % )
        Info: - Micro clock to output delay of source is 0.304 ns
        Info: - Micro setup delay of destination is -0.040 ns
    Info: - Longest register to register delay is 1.234 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N17; Fanout = 4; REG Node = 'freqdiv:inst8|22'
        Info: 2: + IC(0.475 ns) + CELL(0.651 ns) = 1.126 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'freqdiv:inst8|23~22'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.234 ns; Loc. = LCFF_X1_Y5_N11; Fanout = 3; REG Node = 'freqdiv:inst8|23'
        Info: Total cell delay = 0.759 ns ( 61.51 % )
        Info: Total interconnect delay = 0.475 ns ( 38.49 % )
Info: No valid register-to-register data paths exist for clock "clk"
Info: Minimum slack time is 499 ps for clock "PLLT:inst|altpll:altpll_component|_clk0" between source register "freqdiv:inst8|23" and destination register "freqdiv:inst8|23"
    Info: + Shortest register to register delay is 0.501 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N11; Fanout = 3; REG Node = 'freqdiv:inst8|23'
        Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'freqdiv:inst8|23~22'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X1_Y5_N11; Fanout = 3; REG Node = 'freqdiv:inst8|23'
        Info: Total cell delay = 0.501 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.002 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is -2.388 ns
                Info: Clock period of Destination clock "PLLT:inst|altpll:altpll_component|_clk0" is 2.857 ns with  offset of -2.388 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is -2.388 ns
                Info: Clock period of Source clock "PLLT:inst|altpll:altpll_component|_clk0" is 2.857 ns with  offset of -2.388 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "PLLT:inst|altpll:altpll_component|_clk0" to destination register is 2.494 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLLT:inst|altpll:altpll_component|_clk0'
                Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'PLLT:inst|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(0.912 ns) + CELL(0.666 ns) = 2.494 ns; Loc. = LCFF_X1_Y5_N11; Fanout = 3; REG Node = 'freqdiv:inst8|23'
                Info: Total cell delay = 0.666 ns ( 26.70 % )
                Info: Total interconnect delay = 1.828 ns ( 73.30 % )
            Info: - Shortest clock path from clock "PLLT:inst|altpll:altpll_component|_clk0" to source register is 2.494 ns
                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLLT:inst|altpll:altpll_component|_clk0'
                Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'PLLT:inst|altpll:altpll_component|_clk0~clkctrl'
                Info: 3: + IC(0.912 ns) + CELL(0.666 ns) = 2.494 ns; Loc. = LCFF_X1_Y5_N11; Fanout = 3; REG Node = 'freqdiv:inst8|23'
                Info: Total cell delay = 0.666 ns ( 26.70 % )
                Info: Total interconnect delay = 1.828 ns ( 73.30 % )
        Info: - Micro clock to output delay of source is 0.304 ns
        Info: + Micro hold delay of destination is 0.306 ns
Info: tco from clock "clk" to destination pin "C1213" through register "freqdiv:inst8|23" is 4.649 ns
    Info: + Offset between input clock "clk" and output clock "PLLT:inst|altpll:altpll_component|_clk0" is -2.388 ns
    Info: + Longest clock path from clock "PLLT:inst|altpll:altpll_component|_clk0" to source register is 2.494 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLLT:inst|altpll:altpll_component|_clk0'
        Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'PLLT:inst|altpll:altpll_component|_clk0~clkctrl'
        Info: 3: + IC(0.912 ns) + CELL(0.666 ns) = 2.494 ns; Loc. = LCFF_X1_Y5_N11; Fanout = 3; REG Node = 'freqdiv:inst8|23'
        Info: Total cell delay = 0.666 ns ( 26.70 % )
        Info: Total interconnect delay = 1.828 ns ( 73.30 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.239 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N11; Fanout = 3; REG Node = 'freqdiv:inst8|23'
        Info: 2: + IC(1.133 ns) + CELL(3.106 ns) = 4.239 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'C1213'
        Info: Total cell delay = 3.106 ns ( 73.27 % )
        Info: Total interconnect delay = 1.133 ns ( 26.73 % )
Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details.
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Thu Jan 08 16:47:27 2009
    Info: Elapsed time: 00:00:02