📄 plltest.tan.rpt
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Classic Timing Analyzer report for PLLTEST
Thu Jan 08 16:47:26 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'PLLT:inst|altpll:altpll_component|_clk0'
6. Clock Hold: 'PLLT:inst|altpll:altpll_component|_clk0'
7. tco
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+--------------------------------------------------------+----------+----------------------------------+------------------------------------------------+------------------+------------------+-----------------------------------------+-----------------------------------------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+--------------------------------------------------------+----------+----------------------------------+------------------------------------------------+------------------+------------------+-----------------------------------------+-----------------------------------------+--------------+
; Worst-case tco ; N/A ; None ; 4.649 ns ; freqdiv:inst8|23 ; C1213 ; clk ; -- ; 0 ;
; Clock Setup: 'PLLT:inst|altpll:altpll_component|_clk0' ; 1.359 ns ; 350.02 MHz ( period = 2.857 ns ) ; Restricted to 402.58 MHz ( period = 2.484 ns ) ; freqdiv:inst8|22 ; freqdiv:inst8|23 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0 ;
; Clock Hold: 'PLLT:inst|altpll:altpll_component|_clk0' ; 0.499 ns ; 350.02 MHz ( period = 2.857 ns ) ; N/A ; freqdiv:inst8|23 ; freqdiv:inst8|23 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+--------------------------------------------------------+----------+----------------------------------+------------------------------------------------+------------------+------------------+-----------------------------------------+-----------------------------------------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8Q208C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; PLLT:inst|altpll:altpll_component|_clk0 ; ; PLL output ; 350.02 MHz ; 0.000 ns ; 0.000 ns ; clk ; 28 ; 3 ; -2.388 ns ; ;
; clk ; ; User Pin ; 37.5 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'PLLT:inst|altpll:altpll_component|_clk0' ;
+----------+-----------------------------------------------+------------------+------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+----------+-----------------------------------------------+------------------+------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
; 1.359 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; freqdiv:inst8|22 ; freqdiv:inst8|23 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 2.857 ns ; 2.593 ns ; 1.234 ns ;
; 1.363 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; freqdiv:inst8|22 ; freqdiv:inst8|24 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 2.857 ns ; 2.593 ns ; 1.230 ns ;
; 1.405 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; freqdiv:inst8|21 ; freqdiv:inst8|24 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 2.857 ns ; 2.593 ns ; 1.188 ns ;
; 1.827 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; freqdiv:inst8|21 ; freqdiv:inst8|23 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 2.857 ns ; 2.593 ns ; 0.766 ns ;
; 1.830 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; freqdiv:inst8|21 ; freqdiv:inst8|22 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 2.857 ns ; 2.593 ns ; 0.763 ns ;
; 1.846 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; freqdiv:inst8|23 ; freqdiv:inst8|24 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 2.857 ns ; 2.593 ns ; 0.747 ns ;
; 2.092 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; freqdiv:inst8|23 ; freqdiv:inst8|23 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 2.857 ns ; 2.593 ns ; 0.501 ns ;
; 2.092 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; freqdiv:inst8|21 ; freqdiv:inst8|21 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 2.857 ns ; 2.593 ns ; 0.501 ns ;
; 2.092 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; freqdiv:inst8|22 ; freqdiv:inst8|22 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 2.857 ns ; 2.593 ns ; 0.501 ns ;
; 2.092 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; freqdiv:inst8|24 ; freqdiv:inst8|24 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 2.857 ns ; 2.593 ns ; 0.501 ns ;
+----------+-----------------------------------------------+------------------+------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'PLLT:inst|altpll:altpll_component|_clk0' ;
+---------------+------------------+------------------+-----------------------------------------+-----------------------------------------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+---------------+------------------+------------------+-----------------------------------------+-----------------------------------------+----------------------------+----------------------------+--------------------------+
; 0.499 ns ; freqdiv:inst8|23 ; freqdiv:inst8|23 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.002 ns ; 0.501 ns ;
; 0.499 ns ; freqdiv:inst8|21 ; freqdiv:inst8|21 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.002 ns ; 0.501 ns ;
; 0.499 ns ; freqdiv:inst8|22 ; freqdiv:inst8|22 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.002 ns ; 0.501 ns ;
; 0.499 ns ; freqdiv:inst8|24 ; freqdiv:inst8|24 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.002 ns ; 0.501 ns ;
; 0.745 ns ; freqdiv:inst8|23 ; freqdiv:inst8|24 ; PLLT:inst|altpll:altpll_component|_clk0 ; PLLT:inst|altpll:altpll_component|_clk0 ; 0.000 ns ; 0.002 ns ; 0.747 ns ;
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