bit8_portout.tan.qmsg

Source of Grabber Board

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK P0UT\[1\] pout_component:I_portout\|RegQ\[1\] 9.400 ns register " "Info: Minimum tco from clock CLK to destination pin P0UT\[1\] through register pout_component:I_portout\|RegQ\[1\] is 9.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.900 ns + Shortest register " "Info: + Shortest clock path from clock CLK to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns pout_component:I_portout\|RegQ\[1\] 2 REG LC3_C14 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C14; Fanout = 2; REG Node = 'pout_component:I_portout\|RegQ\[1\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "2.000 ns" { CLK pout_component:I_portout|RegQ[1] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|RegQ[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pout_component:I_portout\|RegQ\[1\] 1 REG LC3_C14 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C14; Fanout = 2; REG Node = 'pout_component:I_portout\|RegQ\[1\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { pout_component:I_portout|RegQ[1] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(3.900 ns) 4.600 ns P0UT\[1\] 2 PIN PIN_47 0 " "Info: 2: + IC(0.700 ns) + CELL(3.900 ns) = 4.600 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'P0UT\[1\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "4.600 ns" { pout_component:I_portout|RegQ[1] P0UT[1] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 84.78 % " "Info: Total cell delay = 3.900 ns ( 84.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.700 ns 15.22 % " "Info: Total interconnect delay = 0.700 ns ( 15.22 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "4.600 ns" { pout_component:I_portout|RegQ[1] P0UT[1] } "NODE_NAME" } } }  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|RegQ[1] } "NODE_NAME" } } } { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "4.600 ns" { pout_component:I_portout|RegQ[1] P0UT[1] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 10 21:17:01 2006 " "Info: Processing ended: Wed May 10 21:17:01 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}