bit8_portout.vhd

来自「Source of Grabber Board」· VHDL 代码 · 共 44 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY bit8_PortOut IS
   PORT(
      RESET : IN std_logic;
      CLK   : IN std_logic;
      nCS   : IN std_logic;
      nWR   : IN std_logic;
      DIN   : IN std_logic_vector (7 DOWNTO 0);
      P0UT	: OUT std_logic_vector (7 DOWNTO 0)
   );

END bit8_PortOut;

ARCHITECTURE structure OF bit8_PortOut IS

   -- COMPONENT_DECLARATIONS
      COMPONENT pout_component
         PORT(
            RESET      : IN std_logic;
            CLK        : IN std_logic;
            nWR        : IN std_logic;
            DIN        : IN std_logic_vector (7 DOWNTO 0);
            nCS 	   : IN std_logic;
            POUT       : OUT std_logic_vector (7 DOWNTO 0)
         );
      END COMPONENT;

   BEGIN
      -- COMPONENT INSTANTIATIONS
      I_portout : pout_component
         PORT MAP(
            RESET      => RESET     , 
            CLK        => CLK       , 
			nWR		   => nWR		,
            DIN        => DIN       ,
            nCS	       => nCS		,
            POUT       => P0UT     
         );


   END structure;