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📄 bit8_portout.tan.qmsg

📁 Source of Grabber Board
💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node CLK is an undefined clock" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 7 -1 0 } } { "c:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register pout_component:I_portout\|SynchProc~0 pout_component:I_portout\|RegQ\[0\] 125.0 MHz Internal " "Info: Clock CLK Internal fmax is restricted to 125.0 MHz between source register pout_component:I_portout\|SynchProc~0 and destination register pout_component:I_portout\|RegQ\[0\]" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.300 ns + Longest register register " "Info: + Longest register to register delay is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pout_component:I_portout\|SynchProc~0 1 REG LC1_C15 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C15; Fanout = 16; REG Node = 'pout_component:I_portout\|SynchProc~0'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { pout_component:I_portout|SynchProc~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 3.800 ns pout_component:I_portout\|RegD\[0\]~670 2 COMB LC8_C14 1 " "Info: 2: + IC(1.900 ns) + CELL(1.900 ns) = 3.800 ns; Loc. = LC8_C14; Fanout = 1; COMB Node = 'pout_component:I_portout\|RegD\[0\]~670'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.800 ns" { pout_component:I_portout|SynchProc~0 pout_component:I_portout|RegD[0]~670 } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.900 ns) 5.300 ns pout_component:I_portout\|RegQ\[0\] 3 REG LC2_C14 2 " "Info: 3: + IC(0.600 ns) + CELL(0.900 ns) = 5.300 ns; Loc. = LC2_C14; Fanout = 2; REG Node = 'pout_component:I_portout\|RegQ\[0\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "1.500 ns" { pout_component:I_portout|RegD[0]~670 pout_component:I_portout|RegQ[0] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "5.300 ns" { pout_component:I_portout|SynchProc~0 pout_component:I_portout|RegD[0]~670 pout_component:I_portout|RegQ[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock CLK to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns pout_component:I_portout\|RegQ\[0\] 2 REG LC2_C14 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_C14; Fanout = 2; REG Node = 'pout_component:I_portout\|RegQ\[0\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "2.000 ns" { CLK pout_component:I_portout|RegQ[0] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|RegQ[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.900 ns - Longest register " "Info: - Longest clock path from clock CLK to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns pout_component:I_portout\|SynchProc~0 2 REG LC1_C15 16 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C15; Fanout = 16; REG Node = 'pout_component:I_portout\|SynchProc~0'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "2.000 ns" { CLK pout_component:I_portout|SynchProc~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|SynchProc~0 } "NODE_NAME" } } }  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|RegQ[0] } "NODE_NAME" } } } { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|SynchProc~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "5.300 ns" { pout_component:I_portout|SynchProc~0 pout_component:I_portout|RegD[0]~670 pout_component:I_portout|RegQ[0] } "NODE_NAME" } } } { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|RegQ[0] } "NODE_NAME" } } } { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|SynchProc~0 } "NODE_NAME" } } }  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { pout_component:I_portout|RegQ[0] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "pout_component:I_portout\|RegQ\[7\] nWR CLK 4.600 ns register " "Info: tsu for register pout_component:I_portout\|RegQ\[7\] (data pin = nWR, clock pin = CLK) is 4.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns + Longest pin register " "Info: + Longest pin to register delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns nWR 1 PIN PIN_44 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_44; Fanout = 16; PIN Node = 'nWR'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { nWR } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 5.700 ns pout_component:I_portout\|RegD\[7\]~656 2 COMB LC2_C13 1 " "Info: 2: + IC(1.900 ns) + CELL(1.900 ns) = 5.700 ns; Loc. = LC2_C13; Fanout = 1; COMB Node = 'pout_component:I_portout\|RegD\[7\]~656'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.800 ns" { nWR pout_component:I_portout|RegD[7]~656 } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.900 ns) 7.200 ns pout_component:I_portout\|RegQ\[7\] 3 REG LC5_C13 2 " "Info: 3: + IC(0.600 ns) + CELL(0.900 ns) = 7.200 ns; Loc. = LC5_C13; Fanout = 2; REG Node = 'pout_component:I_portout\|RegQ\[7\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "1.500 ns" { pout_component:I_portout|RegD[7]~656 pout_component:I_portout|RegQ[7] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.700 ns 65.28 % " "Info: Total cell delay = 4.700 ns ( 65.28 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 34.72 % " "Info: Total interconnect delay = 2.500 ns ( 34.72 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "7.200 ns" { nWR pout_component:I_portout|RegD[7]~656 pout_component:I_portout|RegQ[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock CLK to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns pout_component:I_portout\|RegQ\[7\] 2 REG LC5_C13 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_C13; Fanout = 2; REG Node = 'pout_component:I_portout\|RegQ\[7\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "2.000 ns" { CLK pout_component:I_portout|RegQ[7] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|RegQ[7] } "NODE_NAME" } } }  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "7.200 ns" { nWR pout_component:I_portout|RegD[7]~656 pout_component:I_portout|RegQ[7] } "NODE_NAME" } } } { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|RegQ[7] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK P0UT\[0\] pout_component:I_portout\|SynchProc~0 13.300 ns register " "Info: tco from clock CLK to destination pin P0UT\[0\] through register pout_component:I_portout\|SynchProc~0 is 13.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.900 ns + Longest register " "Info: + Longest clock path from clock CLK to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns pout_component:I_portout\|SynchProc~0 2 REG LC1_C15 16 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C15; Fanout = 16; REG Node = 'pout_component:I_portout\|SynchProc~0'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "2.000 ns" { CLK pout_component:I_portout|SynchProc~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|SynchProc~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.500 ns + Longest register pin " "Info: + Longest register to pin delay is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pout_component:I_portout\|SynchProc~0 1 REG LC1_C15 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C15; Fanout = 16; REG Node = 'pout_component:I_portout\|SynchProc~0'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { pout_component:I_portout|SynchProc~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(5.000 ns) 8.500 ns P0UT\[0\] 2 PIN PIN_22 0 " "Info: 2: + IC(3.500 ns) + CELL(5.000 ns) = 8.500 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'P0UT\[0\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "8.500 ns" { pout_component:I_portout|SynchProc~0 P0UT[0] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns 58.82 % " "Info: Total cell delay = 5.000 ns ( 58.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns 41.18 % " "Info: Total interconnect delay = 3.500 ns ( 41.18 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "8.500 ns" { pout_component:I_portout|SynchProc~0 P0UT[0] } "NODE_NAME" } } }  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|SynchProc~0 } "NODE_NAME" } } } { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "8.500 ns" { pout_component:I_portout|SynchProc~0 P0UT[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "pout_component:I_portout\|RegQ\[6\] DIN\[6\] CLK 0.300 ns register " "Info: th for register pout_component:I_portout\|RegQ\[6\] (data pin = DIN\[6\], clock pin = CLK) is 0.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.900 ns + Longest register " "Info: + Longest clock path from clock CLK to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK 1 CLK PIN_43 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns pout_component:I_portout\|RegQ\[6\] 2 REG LC3_C13 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C13; Fanout = 2; REG Node = 'pout_component:I_portout\|RegQ\[6\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "2.000 ns" { CLK pout_component:I_portout|RegQ[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|RegQ[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns DIN\[6\] 1 PIN PIN_1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 1; PIN Node = 'DIN\[6\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "" { DIN[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/bit8_portout.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.400 ns) 5.000 ns pout_component:I_portout\|RegQ\[6\] 2 REG LC3_C13 2 " "Info: 2: + IC(1.700 ns) + CELL(1.400 ns) = 5.000 ns; Loc. = LC3_C13; Fanout = 2; REG Node = 'pout_component:I_portout\|RegQ\[6\]'" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.100 ns" { DIN[6] pout_component:I_portout|RegQ[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.300 ns 66.00 % " "Info: Total cell delay = 3.300 ns ( 66.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 34.00 % " "Info: Total interconnect delay = 1.700 ns ( 34.00 % )" {  } {  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "5.000 ns" { DIN[6] pout_component:I_portout|RegQ[6] } "NODE_NAME" } } }  } 0}  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "3.900 ns" { CLK pout_component:I_portout|RegQ[6] } "NODE_NAME" } } } { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" "" "" { Report "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout_cmp.qrpt" Compiler "bit8_portout" "UNKNOWN" "V1" "D:/UAV/HW/FPGA/uavfpga/bit8_portout/db/bit8_portout.quartus_db" { Floorplan "" "" "5.000 ns" { DIN[6] pout_component:I_portout|RegQ[6] } "NODE_NAME" } } }  } 0}
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