bit8_portout.map.qmsg

Source of Grabber Board

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Web Edition " "Info: Version 4.1 Build 181 06/29/2004 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 10 21:16:53 2006 " "Info: Processing started: Wed May 10 21:16:53 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off bit8_portout -c bit8_portout " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off bit8_portout -c bit8_portout" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bit8_portout.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bit8_portout.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bit8_PortOut-structure " "Info: Found design unit 1: bit8_PortOut-structure" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/bit8_portout.vhd" "bit8_PortOut-structure" "" { Text "D:/UAV/HW/FPGA/uavfpga/bit8_portout/bit8_portout.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 bit8_PortOut " "Info: Found entity 1: bit8_PortOut" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/bit8_portout.vhd" "bit8_PortOut" "" { Text "D:/UAV/HW/FPGA/uavfpga/bit8_portout/bit8_portout.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "pout_component.vhd 2 1 " "Info: Using design file pout_component.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pout_component-rtl " "Info: Found design unit 1: pout_component-rtl" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/pout_component.vhd" "pout_component-rtl" "" { Text "D:/UAV/HW/FPGA/uavfpga/bit8_portout/pout_component.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 pout_component " "Info: Found entity 1: pout_component" {  } { { "D:/UAV/HW/FPGA/uavfpga/bit8_portout/pout_component.vhd" "pout_component" "" { Text "D:/UAV/HW/FPGA/uavfpga/bit8_portout/pout_component.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "Netlist Optimizations " "Warning: Feature Netlist Optimizations is not available with your current license" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer to OR gate or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pout_component:I_portout\|POUT\[7\]~0 " "Warning: Converting TRI node pout_component:I_portout\|POUT\[7\]~0 that feeds logic to an OR gate" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pout_component:I_portout\|POUT\[6\]~1 " "Warning: Converting TRI node pout_component:I_portout\|POUT\[6\]~1 that feeds logic to an OR gate" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pout_component:I_portout\|POUT\[5\]~2 " "Warning: Converting TRI node pout_component:I_portout\|POUT\[5\]~2 that feeds logic to an OR gate" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pout_component:I_portout\|POUT\[4\]~3 " "Warning: Converting TRI node pout_component:I_portout\|POUT\[4\]~3 that feeds logic to an OR gate" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pout_component:I_portout\|POUT\[3\]~4 " "Warning: Converting TRI node pout_component:I_portout\|POUT\[3\]~4 that feeds logic to an OR gate" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pout_component:I_portout\|POUT\[2\]~5 " "Warning: Converting TRI node pout_component:I_portout\|POUT\[2\]~5 that feeds logic to an OR gate" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pout_component:I_portout\|POUT\[1\]~6 " "Warning: Converting TRI node pout_component:I_portout\|POUT\[1\]~6 that feeds logic to an OR gate" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "pout_component:I_portout\|POUT\[0\]~7 " "Warning: Converting TRI node pout_component:I_portout\|POUT\[0\]~7 that feeds logic to an OR gate" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" "" "" { Text "d:/uav/hw/fpga/uavfpga/bit8_portout/pout_component.vhd" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "pout_component:I_portout\|SynchProc~7 pout_component:I_portout\|SynchProc~0 " "Info: Duplicate register pout_component:I_portout\|SynchProc~7 merged to single register pout_component:I_portout\|SynchProc~0" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pout_component:I_portout\|SynchProc~6 pout_component:I_portout\|SynchProc~0 " "Info: Duplicate register pout_component:I_portout\|SynchProc~6 merged to single register pout_component:I_portout\|SynchProc~0" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pout_component:I_portout\|SynchProc~5 pout_component:I_portout\|SynchProc~0 " "Info: Duplicate register pout_component:I_portout\|SynchProc~5 merged to single register pout_component:I_portout\|SynchProc~0" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pout_component:I_portout\|SynchProc~4 pout_component:I_portout\|SynchProc~0 " "Info: Duplicate register pout_component:I_portout\|SynchProc~4 merged to single register pout_component:I_portout\|SynchProc~0" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pout_component:I_portout\|SynchProc~3 pout_component:I_portout\|SynchProc~0 " "Info: Duplicate register pout_component:I_portout\|SynchProc~3 merged to single register pout_component:I_portout\|SynchProc~0" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pout_component:I_portout\|SynchProc~2 pout_component:I_portout\|SynchProc~0 " "Info: Duplicate register pout_component:I_portout\|SynchProc~2 merged to single register pout_component:I_portout\|SynchProc~0" {  } {  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pout_component:I_portout\|SynchProc~1 pout_component:I_portout\|SynchProc~0 " "Info: Duplicate register pout_component:I_portout\|SynchProc~1 merged to single register pout_component:I_portout\|SynchProc~0" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "37 " "Info: Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "17 " "Info: Implemented 17 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 10 21:16:55 2006 " "Info: Processing ended: Wed May 10 21:16:55 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}