bit8_portout.map.rpt

Source of Grabber Board

+-------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+----------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/UAV/HW/FPGA/uavfpga/bit8_portout/bit8_portout.map.eqn.


+--------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                   ;
+--------------------------------------------------------+-----------------+
; File Name                                              ; Used in Netlist ;
+--------------------------------------------------------+-----------------+
; bit8_portout.vhd                                       ; yes             ;
; D:/UAV/HW/FPGA/uavfpga/bit8_portout/pout_component.vhd ; yes             ;
+--------------------------------------------------------+-----------------+


+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                            ;
+---------------------------------+--------------------------------------+
; Resource                        ; Usage                                ;
+---------------------------------+--------------------------------------+
; Logic cells                     ; 17                                   ;
; Total combinational functions   ; 17                                   ;
; Total 4-input functions         ; 16                                   ;
; Total 3-input functions         ; 0                                    ;
; Total 2-input functions         ; 0                                    ;
; Total 1-input functions         ; 0                                    ;
; Total 0-input functions         ; 1                                    ;
; Combinational cells for routing ; 0                                    ;
; Total registers                 ; 9                                    ;
; I/O pins                        ; 20                                   ;
; Maximum fan-out node            ; pout_component:I_portout|SynchProc~0 ;
; Maximum fan-out                 ; 16                                   ;
; Total fan-out                   ; 98                                   ;
; Average fan-out                 ; 2.65                                 ;
+---------------------------------+--------------------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 17    ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 17    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 9     ;
; Number of cells with combinational logic only          ; 8     ;
; Number of cells with registers only                    ; 0     ;
; Number of cells with combinational logic and registers ; 9     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 9     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Web Edition
    Info: Processing started: Wed May 10 21:16:53 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off bit8_portout -c bit8_portout
Info: Found 2 design units, including 1 entities, in source file bit8_portout.vhd
    Info: Found design unit 1: bit8_PortOut-structure
    Info: Found entity 1: bit8_PortOut
Info: Using design file pout_component.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: pout_component-rtl
    Info: Found entity 1: pout_component
Warning: Feature Netlist Optimizations is not available with your current license
Warning: Converted TRI buffer to OR gate or removed OPNDRN
    Warning: Converting TRI node pout_component:I_portout|POUT[7]~0 that feeds logic to an OR gate
    Warning: Converting TRI node pout_component:I_portout|POUT[6]~1 that feeds logic to an OR gate
    Warning: Converting TRI node pout_component:I_portout|POUT[5]~2 that feeds logic to an OR gate
    Warning: Converting TRI node pout_component:I_portout|POUT[4]~3 that feeds logic to an OR gate
    Warning: Converting TRI node pout_component:I_portout|POUT[3]~4 that feeds logic to an OR gate
    Warning: Converting TRI node pout_component:I_portout|POUT[2]~5 that feeds logic to an OR gate
    Warning: Converting TRI node pout_component:I_portout|POUT[1]~6 that feeds logic to an OR gate
    Warning: Converting TRI node pout_component:I_portout|POUT[0]~7 that feeds logic to an OR gate
Info: Duplicate registers merged to single register
    Info: Duplicate register pout_component:I_portout|SynchProc~7 merged to single register pout_component:I_portout|SynchProc~0
    Info: Duplicate register pout_component:I_portout|SynchProc~6 merged to single register pout_component:I_portout|SynchProc~0
    Info: Duplicate register pout_component:I_portout|SynchProc~5 merged to single register pout_component:I_portout|SynchProc~0
    Info: Duplicate register pout_component:I_portout|SynchProc~4 merged to single register pout_component:I_portout|SynchProc~0
    Info: Duplicate register pout_component:I_portout|SynchProc~3 merged to single register pout_component:I_portout|SynchProc~0
    Info: Duplicate register pout_component:I_portout|SynchProc~2 merged to single register pout_component:I_portout|SynchProc~0
    Info: Duplicate register pout_component:I_portout|SynchProc~1 merged to single register pout_component:I_portout|SynchProc~0
Info: Implemented 37 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 8 output pins
    Info: Implemented 17 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Wed May 10 21:16:55 2006
    Info: Elapsed time: 00:00:01