pout_component.vhd

来自「Source of Grabber Board」· VHDL 代码 · 共 53 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY pout_component IS
   PORT(
      RESET       : IN std_logic;
      CLK         : IN std_logic;
	  nWR		  : IN std_logic;
      DIN         : IN std_logic_vector (7 DOWNTO 0);
      nCS 	 	  : IN std_logic;
      POUT        : OUT std_logic_vector (7 DOWNTO 0)
   );

END pout_component;


ARCHITECTURE rtl OF pout_component IS

   SIGNAL    RegD : std_logic_vector(7 DOWNTO 0);
   SIGNAL    RegQ : std_logic_vector(7 DOWNTO 0);


   BEGIN

	  POUT <= RegQ;

      Proc: PROCESS ( nCS,nWR, RegQ, RegD, DIN )

         BEGIN

            IF ( nCS = '0' and nWR = '0' )  THEN
               RegD     <= DIN;
			ELSE
			   RegD     <= RegQ;
            END IF;

         END PROCESS;


      SynchProc: PROCESS ( RESET, CLK )

         BEGIN

            IF (RESET = '1') THEN
               RegQ     <= "ZZZZZZZZ";
            ELSIF ( CLK'EVENT and CLK = '0')  THEN
               RegQ     <= RegD;
            END IF;

         END PROCESS;

   END rtl;