bit8_portout.map.eqn

Source of Grabber Board

--B1_RegQ[7] is pout_component:I_portout|RegQ[7]
--operation mode is normal

B1_RegQ[7]_lut_out = B1L8 # DIN[7] & !nCS & !nWR;
B1_RegQ[7] = DFFEA(B1_RegQ[7]_lut_out, !CLK, !RESET, , , , );


--B1L81Q is pout_component:I_portout|SynchProc~0
--operation mode is normal

B1L81Q_lut_out = VCC;
B1L81Q = DFFEA(B1L81Q_lut_out, !CLK, !RESET, , , , );


--B1_RegQ[6] is pout_component:I_portout|RegQ[6]
--operation mode is normal

B1_RegQ[6]_lut_out = B1L7 # DIN[6] & !nCS & !nWR;
B1_RegQ[6] = DFFEA(B1_RegQ[6]_lut_out, !CLK, !RESET, , , , );


--B1_RegQ[5] is pout_component:I_portout|RegQ[5]
--operation mode is normal

B1_RegQ[5]_lut_out = B1L6 # DIN[5] & !nCS & !nWR;
B1_RegQ[5] = DFFEA(B1_RegQ[5]_lut_out, !CLK, !RESET, , , , );


--B1_RegQ[4] is pout_component:I_portout|RegQ[4]
--operation mode is normal

B1_RegQ[4]_lut_out = B1L5 # DIN[4] & !nCS & !nWR;
B1_RegQ[4] = DFFEA(B1_RegQ[4]_lut_out, !CLK, !RESET, , , , );


--B1_RegQ[3] is pout_component:I_portout|RegQ[3]
--operation mode is normal

B1_RegQ[3]_lut_out = B1L4 # DIN[3] & !nCS & !nWR;
B1_RegQ[3] = DFFEA(B1_RegQ[3]_lut_out, !CLK, !RESET, , , , );


--B1_RegQ[2] is pout_component:I_portout|RegQ[2]
--operation mode is normal

B1_RegQ[2]_lut_out = B1L3 # DIN[2] & !nCS & !nWR;
B1_RegQ[2] = DFFEA(B1_RegQ[2]_lut_out, !CLK, !RESET, , , , );


--B1_RegQ[1] is pout_component:I_portout|RegQ[1]
--operation mode is normal

B1_RegQ[1]_lut_out = B1L2 # DIN[1] & !nCS & !nWR;
B1_RegQ[1] = DFFEA(B1_RegQ[1]_lut_out, !CLK, !RESET, , , , );


--B1_RegQ[0] is pout_component:I_portout|RegQ[0]
--operation mode is normal

B1_RegQ[0]_lut_out = B1L1 # DIN[0] & !nCS & !nWR;
B1_RegQ[0] = DFFEA(B1_RegQ[0]_lut_out, !CLK, !RESET, , , , );


--B1L8 is pout_component:I_portout|RegD[7]~656
--operation mode is normal

B1L8 = B1_RegQ[7] & (nCS # nWR) # !B1_RegQ[7] & !B1L81Q & (nCS # nWR);


--B1L7 is pout_component:I_portout|RegD[6]~658
--operation mode is normal

B1L7 = B1_RegQ[6] & (nCS # nWR) # !B1_RegQ[6] & !B1L81Q & (nCS # nWR);


--B1L6 is pout_component:I_portout|RegD[5]~660
--operation mode is normal

B1L6 = B1_RegQ[5] & (nCS # nWR) # !B1_RegQ[5] & !B1L81Q & (nCS # nWR);


--B1L5 is pout_component:I_portout|RegD[4]~662
--operation mode is normal

B1L5 = B1_RegQ[4] & (nCS # nWR) # !B1_RegQ[4] & !B1L81Q & (nCS # nWR);


--B1L4 is pout_component:I_portout|RegD[3]~664
--operation mode is normal

B1L4 = B1_RegQ[3] & (nCS # nWR) # !B1_RegQ[3] & !B1L81Q & (nCS # nWR);


--B1L3 is pout_component:I_portout|RegD[2]~666
--operation mode is normal

B1L3 = B1_RegQ[2] & (nCS # nWR) # !B1_RegQ[2] & !B1L81Q & (nCS # nWR);


--B1L2 is pout_component:I_portout|RegD[1]~668
--operation mode is normal

B1L2 = B1_RegQ[1] & (nCS # nWR) # !B1_RegQ[1] & !B1L81Q & (nCS # nWR);


--B1L1 is pout_component:I_portout|RegD[0]~670
--operation mode is normal

B1L1 = B1_RegQ[0] & (nCS # nWR) # !B1_RegQ[0] & !B1L81Q & (nCS # nWR);


--nCS is nCS
--operation mode is input

nCS = INPUT();


--nWR is nWR
--operation mode is input

nWR = INPUT();


--DIN[7] is DIN[7]
--operation mode is input

DIN[7] = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--RESET is RESET
--operation mode is input

RESET = INPUT();


--DIN[6] is DIN[6]
--operation mode is input

DIN[6] = INPUT();


--DIN[5] is DIN[5]
--operation mode is input

DIN[5] = INPUT();


--DIN[4] is DIN[4]
--operation mode is input

DIN[4] = INPUT();


--DIN[3] is DIN[3]
--operation mode is input

DIN[3] = INPUT();


--DIN[2] is DIN[2]
--operation mode is input

DIN[2] = INPUT();


--DIN[1] is DIN[1]
--operation mode is input

DIN[1] = INPUT();


--DIN[0] is DIN[0]
--operation mode is input

DIN[0] = INPUT();


--P0UT[7] is P0UT[7]
--operation mode is output

P0UT[7]_tri_out = TRI(B1_RegQ[7], B1L81Q);
P0UT[7] = OUTPUT(P0UT[7]_tri_out);


--P0UT[6] is P0UT[6]
--operation mode is output

P0UT[6]_tri_out = TRI(B1_RegQ[6], B1L81Q);
P0UT[6] = OUTPUT(P0UT[6]_tri_out);


--P0UT[5] is P0UT[5]
--operation mode is output

P0UT[5]_tri_out = TRI(B1_RegQ[5], B1L81Q);
P0UT[5] = OUTPUT(P0UT[5]_tri_out);


--P0UT[4] is P0UT[4]
--operation mode is output

P0UT[4]_tri_out = TRI(B1_RegQ[4], B1L81Q);
P0UT[4] = OUTPUT(P0UT[4]_tri_out);


--P0UT[3] is P0UT[3]
--operation mode is output

P0UT[3]_tri_out = TRI(B1_RegQ[3], B1L81Q);
P0UT[3] = OUTPUT(P0UT[3]_tri_out);


--P0UT[2] is P0UT[2]
--operation mode is output

P0UT[2]_tri_out = TRI(B1_RegQ[2], B1L81Q);
P0UT[2] = OUTPUT(P0UT[2]_tri_out);


--P0UT[1] is P0UT[1]
--operation mode is output

P0UT[1]_tri_out = TRI(B1_RegQ[1], B1L81Q);
P0UT[1] = OUTPUT(P0UT[1]_tri_out);


--P0UT[0] is P0UT[0]
--operation mode is output

P0UT[0]_tri_out = TRI(B1_RegQ[0], B1L81Q);
P0UT[0] = OUTPUT(P0UT[0]_tri_out);