📄 bit8_portout.tan.rpt
字号:
; N/A ; None ; 13.100 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[5] ; CLK ;
; N/A ; None ; 13.100 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[6] ; CLK ;
; N/A ; None ; 13.100 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[7] ; CLK ;
; N/A ; None ; 11.600 ns ; pout_component:I_portout|RegQ[0] ; P0UT[0] ; CLK ;
; N/A ; None ; 10.900 ns ; pout_component:I_portout|RegQ[6] ; P0UT[6] ; CLK ;
; N/A ; None ; 10.700 ns ; pout_component:I_portout|RegQ[3] ; P0UT[3] ; CLK ;
; N/A ; None ; 10.600 ns ; pout_component:I_portout|RegQ[5] ; P0UT[5] ; CLK ;
; N/A ; None ; 10.000 ns ; pout_component:I_portout|RegQ[2] ; P0UT[2] ; CLK ;
; N/A ; None ; 10.000 ns ; pout_component:I_portout|RegQ[7] ; P0UT[7] ; CLK ;
; N/A ; None ; 9.600 ns ; pout_component:I_portout|RegQ[4] ; P0UT[4] ; CLK ;
; N/A ; None ; 9.400 ns ; pout_component:I_portout|RegQ[1] ; P0UT[1] ; CLK ;
+-------+--------------+------------+--------------------------------------+---------+------------+
+------------------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+--------+----------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+--------+----------------------------------+----------+
; N/A ; None ; 0.300 ns ; DIN[6] ; pout_component:I_portout|RegQ[6] ; CLK ;
; N/A ; None ; 0.300 ns ; DIN[7] ; pout_component:I_portout|RegQ[7] ; CLK ;
; N/A ; None ; 0.100 ns ; nWR ; pout_component:I_portout|RegQ[7] ; CLK ;
; N/A ; None ; 0.100 ns ; nWR ; pout_component:I_portout|RegQ[6] ; CLK ;
; N/A ; None ; 0.100 ns ; nWR ; pout_component:I_portout|RegQ[5] ; CLK ;
; N/A ; None ; 0.100 ns ; nWR ; pout_component:I_portout|RegQ[4] ; CLK ;
; N/A ; None ; 0.100 ns ; nWR ; pout_component:I_portout|RegQ[3] ; CLK ;
; N/A ; None ; 0.100 ns ; nWR ; pout_component:I_portout|RegQ[2] ; CLK ;
; N/A ; None ; 0.100 ns ; nWR ; pout_component:I_portout|RegQ[1] ; CLK ;
; N/A ; None ; 0.100 ns ; nWR ; pout_component:I_portout|RegQ[0] ; CLK ;
; N/A ; None ; 0.100 ns ; nCS ; pout_component:I_portout|RegQ[7] ; CLK ;
; N/A ; None ; 0.100 ns ; nCS ; pout_component:I_portout|RegQ[6] ; CLK ;
; N/A ; None ; 0.100 ns ; nCS ; pout_component:I_portout|RegQ[5] ; CLK ;
; N/A ; None ; 0.100 ns ; nCS ; pout_component:I_portout|RegQ[4] ; CLK ;
; N/A ; None ; 0.100 ns ; nCS ; pout_component:I_portout|RegQ[3] ; CLK ;
; N/A ; None ; 0.100 ns ; nCS ; pout_component:I_portout|RegQ[2] ; CLK ;
; N/A ; None ; 0.100 ns ; nCS ; pout_component:I_portout|RegQ[1] ; CLK ;
; N/A ; None ; 0.100 ns ; nCS ; pout_component:I_portout|RegQ[0] ; CLK ;
; N/A ; None ; -1.700 ns ; DIN[2] ; pout_component:I_portout|RegQ[2] ; CLK ;
; N/A ; None ; -1.700 ns ; DIN[4] ; pout_component:I_portout|RegQ[4] ; CLK ;
; N/A ; None ; -1.800 ns ; DIN[0] ; pout_component:I_portout|RegQ[0] ; CLK ;
; N/A ; None ; -1.800 ns ; DIN[1] ; pout_component:I_portout|RegQ[1] ; CLK ;
; N/A ; None ; -1.800 ns ; DIN[3] ; pout_component:I_portout|RegQ[3] ; CLK ;
; N/A ; None ; -1.800 ns ; DIN[5] ; pout_component:I_portout|RegQ[5] ; CLK ;
+---------------+-------------+-----------+--------+----------------------------------+----------+
+-----------------------------------------------------------------------------------------------------------------+
; Minimum tco ;
+---------------+------------------+----------------+--------------------------------------+---------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+--------------------------------------+---------+------------+
; N/A ; None ; 9.400 ns ; pout_component:I_portout|RegQ[1] ; P0UT[1] ; CLK ;
; N/A ; None ; 9.600 ns ; pout_component:I_portout|RegQ[4] ; P0UT[4] ; CLK ;
; N/A ; None ; 10.000 ns ; pout_component:I_portout|RegQ[7] ; P0UT[7] ; CLK ;
; N/A ; None ; 10.000 ns ; pout_component:I_portout|RegQ[2] ; P0UT[2] ; CLK ;
; N/A ; None ; 10.600 ns ; pout_component:I_portout|RegQ[5] ; P0UT[5] ; CLK ;
; N/A ; None ; 10.700 ns ; pout_component:I_portout|RegQ[3] ; P0UT[3] ; CLK ;
; N/A ; None ; 10.900 ns ; pout_component:I_portout|RegQ[6] ; P0UT[6] ; CLK ;
; N/A ; None ; 11.600 ns ; pout_component:I_portout|RegQ[0] ; P0UT[0] ; CLK ;
; N/A ; None ; 13.100 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[7] ; CLK ;
; N/A ; None ; 13.100 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[6] ; CLK ;
; N/A ; None ; 13.100 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[5] ; CLK ;
; N/A ; None ; 13.100 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[2] ; CLK ;
; N/A ; None ; 13.100 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[1] ; CLK ;
; N/A ; None ; 13.200 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[3] ; CLK ;
; N/A ; None ; 13.300 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[4] ; CLK ;
; N/A ; None ; 13.300 ns ; pout_component:I_portout|SynchProc~0 ; P0UT[0] ; CLK ;
+---------------+------------------+----------------+--------------------------------------+---------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.1 Build 181 06/29/2004 SJ Web Edition
Info: Processing started: Wed May 10 21:17:01 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off bit8_portout -c bit8_portout
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
Info: Clock CLK Internal fmax is restricted to 125.0 MHz between source register pout_component:I_portout|SynchProc~0 and destination register pout_component:I_portout|RegQ[0]
Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 5.300 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C15; Fanout = 16; REG Node = 'pout_component:I_portout|SynchProc~0'
Info: 2: + IC(1.900 ns) + CELL(1.900 ns) = 3.800 ns; Loc. = LC8_C14; Fanout = 1; COMB Node = 'pout_component:I_portout|RegD[0]~670'
Info: 3: + IC(0.600 ns) + CELL(0.900 ns) = 5.300 ns; Loc. = LC2_C14; Fanout = 2; REG Node = 'pout_component:I_portout|RegQ[0]'
Info: Total cell delay = 2.800 ns ( 52.83 % )
Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock CLK to destination register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_C14; Fanout = 2; REG Node = 'pout_component:I_portout|RegQ[0]'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: - Longest clock path from clock CLK to source register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C15; Fanout = 16; REG Node = 'pout_component:I_portout|SynchProc~0'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: + Micro clock to output delay of source is 0.900 ns
Info: + Micro setup delay of destination is 1.300 ns
Info: tsu for register pout_component:I_portout|RegQ[7] (data pin = nWR, clock pin = CLK) is 4.600 ns
Info: + Longest pin to register delay is 7.200 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_44; Fanout = 16; PIN Node = 'nWR'
Info: 2: + IC(1.900 ns) + CELL(1.900 ns) = 5.700 ns; Loc. = LC2_C13; Fanout = 1; COMB Node = 'pout_component:I_portout|RegD[7]~656'
Info: 3: + IC(0.600 ns) + CELL(0.900 ns) = 7.200 ns; Loc. = LC5_C13; Fanout = 2; REG Node = 'pout_component:I_portout|RegQ[7]'
Info: Total cell delay = 4.700 ns ( 65.28 % )
Info: Total interconnect delay = 2.500 ns ( 34.72 % )
Info: + Micro setup delay of destination is 1.300 ns
Info: - Shortest clock path from clock CLK to destination register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_C13; Fanout = 2; REG Node = 'pout_component:I_portout|RegQ[7]'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: tco from clock CLK to destination pin P0UT[0] through register pout_component:I_portout|SynchProc~0 is 13.300 ns
Info: + Longest clock path from clock CLK to source register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C15; Fanout = 16; REG Node = 'pout_component:I_portout|SynchProc~0'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: + Micro clock to output delay of source is 0.900 ns
Info: + Longest register to pin delay is 8.500 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C15; Fanout = 16; REG Node = 'pout_component:I_portout|SynchProc~0'
Info: 2: + IC(3.500 ns) + CELL(5.000 ns) = 8.500 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'P0UT[0]'
Info: Total cell delay = 5.000 ns ( 58.82 % )
Info: Total interconnect delay = 3.500 ns ( 41.18 % )
Info: th for register pout_component:I_portout|RegQ[6] (data pin = DIN[6], clock pin = CLK) is 0.300 ns
Info: + Longest clock path from clock CLK to destination register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C13; Fanout = 2; REG Node = 'pout_component:I_portout|RegQ[6]'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: + Micro hold delay of destination is 1.400 ns
Info: - Shortest pin to register delay is 5.000 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 1; PIN Node = 'DIN[6]'
Info: 2: + IC(1.700 ns) + CELL(1.400 ns) = 5.000 ns; Loc. = LC3_C13; Fanout = 2; REG Node = 'pout_component:I_portout|RegQ[6]'
Info: Total cell delay = 3.300 ns ( 66.00 % )
Info: Total interconnect delay = 1.700 ns ( 34.00 % )
Info: Minimum tco from clock CLK to destination pin P0UT[1] through register pout_component:I_portout|RegQ[1] is 9.400 ns
Info: + Shortest clock path from clock CLK to source register is 3.900 ns
Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'CLK'
Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C14; Fanout = 2; REG Node = 'pout_component:I_portout|RegQ[1]'
Info: Total cell delay = 1.900 ns ( 48.72 % )
Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: + Micro clock to output delay of source is 0.900 ns
Info: + Shortest register to pin delay is 4.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C14; Fanout = 2; REG Node = 'pout_component:I_portout|RegQ[1]'
Info: 2: + IC(0.700 ns) + CELL(3.900 ns) = 4.600 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'P0UT[1]'
Info: Total cell delay = 3.900 ns ( 84.78 % )
Info: Total interconnect delay = 0.700 ns ( 15.22 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Wed May 10 21:17:01 2006
Info: Elapsed time: 00:00:00
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