graber.map.eqn

Source of Grabber Board

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--E1_15 is 74157:inst11|15
--operation mode is normal

E1_15 = R/W_DSP & (!A0_PWM1);

--E1L2 is 74157:inst11|15~7
--operation mode is normal

E1L2 = R/W_DSP & (!A0_PWM1);


--E1_19 is 74157:inst11|19
--operation mode is normal

E1_19 = A0_PWM1 # DSP_ADDR[18] & (!Zone2);

--E1L6 is 74157:inst11|19~0
--operation mode is normal

E1L6 = A0_PWM1 # DSP_ADDR[18] & (!Zone2);


--E1L3 is 74157:inst11|17~14
--operation mode is normal

E1L3 = !A0_PWM1 & (DSP_ADDR[18] # Zone2);

--E1L4 is 74157:inst11|17~15
--operation mode is normal

E1L4 = !A0_PWM1 & (DSP_ADDR[18] # Zone2);


--B1_24 is CLOCK:inst45|freqdiv:inst7|24
--operation mode is normal

B1_24_lut_out = !B1_24;
B1_24 = DFFEA(B1_24_lut_out, B2_24, , , B1_31, , );

--B1L8Q is CLOCK:inst45|freqdiv:inst7|24~2
--operation mode is normal

B1L8Q = B1_24;


--K1_q[17] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[17]
--operation mode is clrb_cntr

K1_q[17]_lut_out = (K1_q[17] $ (HREF & K1L35)) & VCC;
K1_q[17] = DFFEA(K1_q[17]_lut_out, LLC2, VREF, , HREF, , );

--K1L73Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[17]~0
--operation mode is clrb_cntr

K1L73Q = K1_q[17];


--H1L35 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[17]~72
--operation mode is normal

H1L35 = A0_PWM1 & K1_q[17] # !A0_PWM1 & (DSP_ADDR[17]);

--H1L36 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[17]~90
--operation mode is normal

H1L36 = A0_PWM1 & K1_q[17] # !A0_PWM1 & (DSP_ADDR[17]);


--K1_q[16] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[16]
--operation mode is clrb_cntr

K1_q[16]_lut_out = (K1_q[16] $ (HREF & K1L33)) & VCC;
K1_q[16] = DFFEA(K1_q[16]_lut_out, LLC2, VREF, , HREF, , );

--K1L71Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[16]~1
--operation mode is clrb_cntr

K1L71Q = K1_q[16];

--K1L35 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT
--operation mode is clrb_cntr

K1L35 = CARRY(K1_q[16] & (K1L33));


--H1L33 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[16]~73
--operation mode is normal

H1L33 = A0_PWM1 & K1_q[16] # !A0_PWM1 & (DSP_ADDR[16]);

--H1L34 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[16]~91
--operation mode is normal

H1L34 = A0_PWM1 & K1_q[16] # !A0_PWM1 & (DSP_ADDR[16]);


--K1_q[15] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

K1_q[15]_lut_out = (K1_q[15] $ (HREF & K1L31)) & VCC;
K1_q[15] = DFFEA(K1_q[15]_lut_out, LLC2, VREF, , HREF, , );

--K1L69Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[15]~2
--operation mode is clrb_cntr

K1L69Q = K1_q[15];

--K1L33 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT
--operation mode is clrb_cntr

K1L33 = CARRY(K1_q[15] & (K1L31));


--H1L31 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[15]~74
--operation mode is normal

H1L31 = A0_PWM1 & K1_q[15] # !A0_PWM1 & (DSP_ADDR[15]);

--H1L32 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[15]~92
--operation mode is normal

H1L32 = A0_PWM1 & K1_q[15] # !A0_PWM1 & (DSP_ADDR[15]);


--K1_q[14] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

K1_q[14]_lut_out = (K1_q[14] $ (HREF & K1L29)) & VCC;
K1_q[14] = DFFEA(K1_q[14]_lut_out, LLC2, VREF, , HREF, , );

--K1L67Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[14]~3
--operation mode is clrb_cntr

K1L67Q = K1_q[14];

--K1L31 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

K1L31 = CARRY(K1_q[14] & (K1L29));


--H1L29 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[14]~75
--operation mode is normal

H1L29 = A0_PWM1 & K1_q[14] # !A0_PWM1 & (DSP_ADDR[14]);

--H1L30 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[14]~93
--operation mode is normal

H1L30 = A0_PWM1 & K1_q[14] # !A0_PWM1 & (DSP_ADDR[14]);


--K1_q[13] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is clrb_cntr

K1_q[13]_lut_out = (K1_q[13] $ (HREF & K1L27)) & VCC;
K1_q[13] = DFFEA(K1_q[13]_lut_out, LLC2, VREF, , HREF, , );

--K1L65Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[13]~4
--operation mode is clrb_cntr

K1L65Q = K1_q[13];

--K1L29 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is clrb_cntr

K1L29 = CARRY(K1_q[13] & (K1L27));


--H1L27 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[13]~76
--operation mode is normal

H1L27 = A0_PWM1 & K1_q[13] # !A0_PWM1 & (DSP_ADDR[13]);

--H1L28 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[13]~94
--operation mode is normal

H1L28 = A0_PWM1 & K1_q[13] # !A0_PWM1 & (DSP_ADDR[13]);


--K1_q[12] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[12]
--operation mode is clrb_cntr

K1_q[12]_lut_out = (K1_q[12] $ (HREF & K1L25)) & VCC;
K1_q[12] = DFFEA(K1_q[12]_lut_out, LLC2, VREF, , HREF, , );

--K1L63Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[12]~5
--operation mode is clrb_cntr

K1L63Q = K1_q[12];

--K1L27 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is clrb_cntr

K1L27 = CARRY(K1_q[12] & (K1L25));


--H1L25 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[12]~77
--operation mode is normal

H1L25 = A0_PWM1 & K1_q[12] # !A0_PWM1 & (DSP_ADDR[12]);

--H1L26 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[12]~95
--operation mode is normal

H1L26 = A0_PWM1 & K1_q[12] # !A0_PWM1 & (DSP_ADDR[12]);


--K1_q[11] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[11]
--operation mode is clrb_cntr

K1_q[11]_lut_out = (K1_q[11] $ (HREF & K1L23)) & VCC;
K1_q[11] = DFFEA(K1_q[11]_lut_out, LLC2, VREF, , HREF, , );

--K1L61Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[11]~6
--operation mode is clrb_cntr

K1L61Q = K1_q[11];

--K1L25 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is clrb_cntr

K1L25 = CARRY(K1_q[11] & (K1L23));


--H1L23 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[11]~78
--operation mode is normal

H1L23 = A0_PWM1 & K1_q[11] # !A0_PWM1 & (DSP_ADDR[11]);

--H1L24 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[11]~96
--operation mode is normal

H1L24 = A0_PWM1 & K1_q[11] # !A0_PWM1 & (DSP_ADDR[11]);


--K1_q[10] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

K1_q[10]_lut_out = (K1_q[10] $ (HREF & K1L21)) & VCC;
K1_q[10] = DFFEA(K1_q[10]_lut_out, LLC2, VREF, , HREF, , );

--K1L59Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[10]~7
--operation mode is clrb_cntr

K1L59Q = K1_q[10];

--K1L23 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is clrb_cntr

K1L23 = CARRY(K1_q[10] & (K1L21));


--H1L21 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[10]~79
--operation mode is normal

H1L21 = A0_PWM1 & K1_q[10] # !A0_PWM1 & (DSP_ADDR[10]);

--H1L22 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[10]~97
--operation mode is normal

H1L22 = A0_PWM1 & K1_q[10] # !A0_PWM1 & (DSP_ADDR[10]);


--K1_q[9] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

K1_q[9]_lut_out = (K1_q[9] $ (HREF & K1L19)) & VCC;
K1_q[9] = DFFEA(K1_q[9]_lut_out, LLC2, VREF, , HREF, , );

--K1L57Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[9]~8
--operation mode is clrb_cntr

K1L57Q = K1_q[9];

--K1L21 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

K1L21 = CARRY(K1_q[9] & (K1L19));


--H1L19 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[9]~80
--operation mode is normal

H1L19 = A0_PWM1 & K1_q[9] # !A0_PWM1 & (DSP_ADDR[9]);

--H1L20 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[9]~98
--operation mode is normal

H1L20 = A0_PWM1 & K1_q[9] # !A0_PWM1 & (DSP_ADDR[9]);


--K1_q[8] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

K1_q[8]_lut_out = (K1_q[8] $ (HREF & K1L17)) & VCC;
K1_q[8] = DFFEA(K1_q[8]_lut_out, LLC2, VREF, , HREF, , );

--K1L55Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[8]~9
--operation mode is clrb_cntr

K1L55Q = K1_q[8];

--K1L19 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

K1L19 = CARRY(K1_q[8] & (K1L17));


--H1L17 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[8]~81
--operation mode is normal

H1L17 = A0_PWM1 & K1_q[8] # !A0_PWM1 & (DSP_ADDR[8]);

--H1L18 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[8]~99
--operation mode is normal

H1L18 = A0_PWM1 & K1_q[8] # !A0_PWM1 & (DSP_ADDR[8]);


--K1_q[7] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

K1_q[7]_lut_out = (K1_q[7] $ (HREF & K1L15)) & VCC;
K1_q[7] = DFFEA(K1_q[7]_lut_out, LLC2, VREF, , HREF, , );

--K1L53Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[7]~10
--operation mode is clrb_cntr

K1L53Q = K1_q[7];

--K1L17 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

K1L17 = CARRY(K1_q[7] & (K1L15));


--H1L15 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[7]~82
--operation mode is normal

H1L15 = A0_PWM1 & K1_q[7] # !A0_PWM1 & (DSP_ADDR[7]);

--H1L16 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[7]~100
--operation mode is normal

H1L16 = A0_PWM1 & K1_q[7] # !A0_PWM1 & (DSP_ADDR[7]);


--K1_q[6] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

K1_q[6]_lut_out = (K1_q[6] $ (HREF & K1L13)) & VCC;
K1_q[6] = DFFEA(K1_q[6]_lut_out, LLC2, VREF, , HREF, , );

--K1L51Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[6]~11
--operation mode is clrb_cntr

K1L51Q = K1_q[6];

--K1L15 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

K1L15 = CARRY(K1_q[6] & (K1L13));


--H1L13 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[6]~83
--operation mode is normal

H1L13 = A0_PWM1 & K1_q[6] # !A0_PWM1 & (DSP_ADDR[6]);

--H1L14 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[6]~101
--operation mode is normal

H1L14 = A0_PWM1 & K1_q[6] # !A0_PWM1 & (DSP_ADDR[6]);


--K1_q[5] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

K1_q[5]_lut_out = (K1_q[5] $ (HREF & K1L11)) & VCC;
K1_q[5] = DFFEA(K1_q[5]_lut_out, LLC2, VREF, , HREF, , );

--K1L49Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[5]~12
--operation mode is clrb_cntr

K1L49Q = K1_q[5];

--K1L13 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

K1L13 = CARRY(K1_q[5] & (K1L11));


--H1L11 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[5]~84
--operation mode is normal

H1L11 = A0_PWM1 & K1_q[5] # !A0_PWM1 & (DSP_ADDR[5]);

--H1L12 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[5]~102
--operation mode is normal

H1L12 = A0_PWM1 & K1_q[5] # !A0_PWM1 & (DSP_ADDR[5]);


--K1_q[4] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

K1_q[4]_lut_out = (K1_q[4] $ (HREF & K1L9)) & VCC;
K1_q[4] = DFFEA(K1_q[4]_lut_out, LLC2, VREF, , HREF, , );

--K1L47Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[4]~13
--operation mode is clrb_cntr

K1L47Q = K1_q[4];

--K1L11 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

K1L11 = CARRY(K1_q[4] & (K1L9));


--H1L9 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[4]~85
--operation mode is normal

H1L9 = A0_PWM1 & K1_q[4] # !A0_PWM1 & (DSP_ADDR[4]);

--H1L10 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[4]~103
--operation mode is normal

H1L10 = A0_PWM1 & K1_q[4] # !A0_PWM1 & (DSP_ADDR[4]);


--K1_q[3] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

K1_q[3]_lut_out = (K1_q[3] $ (HREF & K1L7)) & VCC;
K1_q[3] = DFFEA(K1_q[3]_lut_out, LLC2, VREF, , HREF, , );

--K1L45Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~14
--operation mode is clrb_cntr

K1L45Q = K1_q[3];

--K1L9 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

K1L9 = CARRY(K1_q[3] & (K1L7));


--H1L7 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[3]~86
--operation mode is normal

H1L7 = A0_PWM1 & K1_q[3] # !A0_PWM1 & (DSP_ADDR[3]);

--H1L8 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[3]~104
--operation mode is normal

H1L8 = A0_PWM1 & K1_q[3] # !A0_PWM1 & (DSP_ADDR[3]);


--K1_q[2] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

K1_q[2]_lut_out = (K1_q[2] $ (HREF & K1L5)) & VCC;
K1_q[2] = DFFEA(K1_q[2]_lut_out, LLC2, VREF, , HREF, , );

--K1L43Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~15
--operation mode is clrb_cntr

K1L43Q = K1_q[2];

--K1L7 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

K1L7 = CARRY(K1_q[2] & (K1L5));


--H1L5 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[2]~87
--operation mode is normal

H1L5 = A0_PWM1 & K1_q[2] # !A0_PWM1 & (DSP_ADDR[2]);

--H1L6 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[2]~105
--operation mode is normal

H1L6 = A0_PWM1 & K1_q[2] # !A0_PWM1 & (DSP_ADDR[2]);


--K1_q[1] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

K1_q[1]_lut_out = (K1_q[1] $ (HREF & K1L3)) & VCC;
K1_q[1] = DFFEA(K1_q[1]_lut_out, LLC2, VREF, , HREF, , );

--K1L41Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~16
--operation mode is clrb_cntr

K1L41Q = K1_q[1];

--K1L5 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

K1L5 = CARRY(K1_q[1] & (K1L3));


--H1L3 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[1]~88
--operation mode is normal

H1L3 = A0_PWM1 & K1_q[1] # !A0_PWM1 & (DSP_ADDR[1]);

--H1L4 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[1]~106
--operation mode is normal

H1L4 = A0_PWM1 & K1_q[1] # !A0_PWM1 & (DSP_ADDR[1]);


--K1_q[0] is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

K1_q[0]_lut_out = (HREF $ K1_q[0]) & VCC;
K1_q[0] = DFFEA(K1_q[0]_lut_out, LLC2, VREF, , HREF, , );

--K1L39Q is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~17
--operation mode is clrb_cntr

K1L39Q = K1_q[0];

--K1L3 is addr_part:inst6|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

K1L3 = CARRY(K1_q[0]);


--H1L1 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[0]~89
--operation mode is normal

H1L1 = A0_PWM1 & K1_q[0] # !A0_PWM1 & (DSP_ADDR[0]);

--H1L2 is addr_part:inst6|addr_sec:U2|RAM_ADDR_I[0]~107
--operation mode is normal

H1L2 = A0_PWM1 & K1_q[0] # !A0_PWM1 & (DSP_ADDR[0]);


--B2_24 is CLOCK:inst45|freqdiv:inst20|24
--operation mode is normal

B2_24_lut_out = !B2_24;
B2_24 = DFFEA(B2_24_lut_out, B3_24, , , B2_31, , );

--B2L8Q is CLOCK:inst45|freqdiv:inst20|24~2
--operation mode is normal

B2L8Q = B2_24;


--B1_23 is CLOCK:inst45|freqdiv:inst7|23
--operation mode is normal

B1_23_lut_out = !B1_23;
B1_23 = DFFEA(B1_23_lut_out, B2_24, , , B1_30, , );

--B1L6Q is CLOCK:inst45|freqdiv:inst7|23~2
--operation mode is normal

B1L6Q = B1_23;


--B1_22 is CLOCK:inst45|freqdiv:inst7|22
--operation mode is normal

B1_22_lut_out = !B1_22;
B1_22 = DFFEA(B1_22_lut_out, B2_24, , , B1_21, , );

--B1L4Q is CLOCK:inst45|freqdiv:inst7|22~2
--operation mode is normal

B1L4Q = B1_22;


--B1_21 is CLOCK:inst45|freqdiv:inst7|21
--operation mode is normal

B1_21_lut_out = !B1_21;
B1_21 = DFFEA(B1_21_lut_out, B2_24, , , , , );

--B1L2Q is CLOCK:inst45|freqdiv:inst7|21~2
--operation mode is normal