graber.hier_info

Source of Grabber Board

|graber
RAM_WE <= 74157:inst11.Y1
R/W_DSP => 74157:inst11.B1
A0_PWM1 => 74157:inst11.SEL
A0_PWM1 => addr_part:inst8.SEC
Zone2 => 74157:inst11.B2
Zone2 => 74157:inst11.B3
Zone2 => bit8_PortIn:inst5.DSP_nCS
Zone2 => bit8_PortIn:inst4.DSP_nCS
H1 => 74157:inst11.B4
H1 => CLOCK:inst45.CLKIN
H1 => bit8_PortIn:inst5.CLK_H1
H1 => bit8_PortIn:inst4.CLK_H1
RAM2_CS <= 74157:inst11.Y3
RAM1_CS <= 74157:inst11.Y2
LED_OUT <= led.DB_MAX_OUTPUT_PORT_TYPE
TEST <= 74157:inst11.Y4
DSP[0] <= bit8_PortIn:inst4.D[0]
DSP[1] <= bit8_PortIn:inst4.D[1]
DSP[2] <= bit8_PortIn:inst4.D[2]
DSP[3] <= bit8_PortIn:inst4.D[3]
DSP[4] <= bit8_PortIn:inst4.D[4]
DSP[5] <= bit8_PortIn:inst4.D[5]
DSP[6] <= bit8_PortIn:inst4.D[6]
DSP[7] <= bit8_PortIn:inst4.D[7]
DSP[8] <= bit8_PortIn:inst5.D[0]
DSP[9] <= bit8_PortIn:inst5.D[1]
DSP[10] <= bit8_PortIn:inst5.D[2]
DSP[11] <= bit8_PortIn:inst5.D[3]
DSP[12] <= bit8_PortIn:inst5.D[4]
DSP[13] <= bit8_PortIn:inst5.D[5]
DSP[14] <= bit8_PortIn:inst5.D[6]
DSP[15] <= bit8_PortIn:inst5.D[7]
RD_ => bit8_PortIn:inst5.-IORD
RD_ => bit8_PortIn:inst4.-IORD
RAM[0] => bit8_PortIn:inst4.IN[0]
RAM[1] => bit8_PortIn:inst4.IN[1]
RAM[2] => bit8_PortIn:inst4.IN[2]
RAM[3] => bit8_PortIn:inst4.IN[3]
RAM[4] => bit8_PortIn:inst4.IN[4]
RAM[5] => bit8_PortIn:inst4.IN[5]
RAM[6] => bit8_PortIn:inst4.IN[6]
RAM[7] => bit8_PortIn:inst4.IN[7]
RAM[8] => bit8_PortIn:inst5.IN[0]
RAM[9] => bit8_PortIn:inst5.IN[1]
RAM[10] => bit8_PortIn:inst5.IN[2]
RAM[11] => bit8_PortIn:inst5.IN[3]
RAM[12] => bit8_PortIn:inst5.IN[4]
RAM[13] => bit8_PortIn:inst5.IN[5]
RAM[14] => bit8_PortIn:inst5.IN[6]
RAM[15] => bit8_PortIn:inst5.IN[7]
RAM_ADDR[0] <= addr_part:inst8.RAM_ADDR[0]
RAM_ADDR[1] <= addr_part:inst8.RAM_ADDR[1]
RAM_ADDR[2] <= addr_part:inst8.RAM_ADDR[2]
RAM_ADDR[3] <= addr_part:inst8.RAM_ADDR[3]
RAM_ADDR[4] <= addr_part:inst8.RAM_ADDR[4]
RAM_ADDR[5] <= addr_part:inst8.RAM_ADDR[5]
RAM_ADDR[6] <= addr_part:inst8.RAM_ADDR[6]
RAM_ADDR[7] <= addr_part:inst8.RAM_ADDR[7]
RAM_ADDR[8] <= addr_part:inst8.RAM_ADDR[8]
RAM_ADDR[9] <= addr_part:inst8.RAM_ADDR[9]
RAM_ADDR[10] <= addr_part:inst8.RAM_ADDR[10]
RAM_ADDR[11] <= addr_part:inst8.RAM_ADDR[11]
RAM_ADDR[12] <= addr_part:inst8.RAM_ADDR[12]
RAM_ADDR[13] <= addr_part:inst8.RAM_ADDR[13]
RAM_ADDR[14] <= addr_part:inst8.RAM_ADDR[14]
RAM_ADDR[15] <= addr_part:inst8.RAM_ADDR[15]
RAM_ADDR[16] <= addr_part:inst8.RAM_ADDR[16]
RAM_ADDR[17] <= addr_part:inst8.RAM_ADDR[17]
RAM_ADDR[18] <= addr_part:inst8.RAM_ADDR[18]
LLC2 => addr_part:inst8.LLC2
HREF => addr_part:inst8.HREF
VREF => addr_part:inst8.VREF
DSP_ADDR[0] => addr_part:inst8.DSP_ADDR[0]
DSP_ADDR[1] => addr_part:inst8.DSP_ADDR[1]
DSP_ADDR[2] => addr_part:inst8.DSP_ADDR[2]
DSP_ADDR[3] => addr_part:inst8.DSP_ADDR[3]
DSP_ADDR[4] => addr_part:inst8.DSP_ADDR[4]
DSP_ADDR[5] => addr_part:inst8.DSP_ADDR[5]
DSP_ADDR[6] => addr_part:inst8.DSP_ADDR[6]
DSP_ADDR[7] => addr_part:inst8.DSP_ADDR[7]
DSP_ADDR[8] => addr_part:inst8.DSP_ADDR[8]
DSP_ADDR[9] => addr_part:inst8.DSP_ADDR[9]
DSP_ADDR[10] => addr_part:inst8.DSP_ADDR[10]
DSP_ADDR[11] => addr_part:inst8.DSP_ADDR[11]
DSP_ADDR[12] => addr_part:inst8.DSP_ADDR[12]
DSP_ADDR[13] => addr_part:inst8.DSP_ADDR[13]
DSP_ADDR[14] => addr_part:inst8.DSP_ADDR[14]
DSP_ADDR[15] => addr_part:inst8.DSP_ADDR[15]
DSP_ADDR[16] => addr_part:inst8.DSP_ADDR[16]
DSP_ADDR[17] => addr_part:inst8.DSP_ADDR[17]
DSP_ADDR[18] => addr_part:inst8.DSP_ADDR[18]
WE_ => ~NO_FANOUT~


|graber|74157:inst11
Y4 <= 25.DB_MAX_OUTPUT_PORT_TYPE
A4 => 20.IN0
GN => 12.IN0
GN => 13.IN0
SEL => 12.IN1
SEL => 1.IN0
B4 => 21.IN0
Y3 <= 24.DB_MAX_OUTPUT_PORT_TYPE
A3 => 18.IN0
B3 => 19.IN0
Y2 <= 23.DB_MAX_OUTPUT_PORT_TYPE
A2 => 16.IN0
B2 => 17.IN0
Y1 <= 22.DB_MAX_OUTPUT_PORT_TYPE
A1 => 14.IN0
B1 => 15.IN0


|graber|CLOCK:inst45
LED <= freqdiv:inst7.DV16
CLKIN => freqdiv:inst1.CLK
BootCLK <= freqdiv:inst7.DV4
CLK_10M <= freqdiv:inst1.DV8
CLK_ADC <= freqdiv:inst3.DV2
CLK_8251 <= freqdiv:inst3.DV4
CLK_TXRX <= freqdiv:inst6.DV4


|graber|CLOCK:inst45|freqdiv:inst7
DV16 <= 24.DB_MAX_OUTPUT_PORT_TYPE
CLR => 20.IN0
G => 29.IN0
G => 21~0.IN0
CLK => 21.CLK
CLK => 22.CLK
CLK => 23.CLK
CLK => 24.CLK
DV8 <= 23.DB_MAX_OUTPUT_PORT_TYPE
DV4 <= 22.DB_MAX_OUTPUT_PORT_TYPE
DV2 <= 21.DB_MAX_OUTPUT_PORT_TYPE


|graber|CLOCK:inst45|freqdiv:inst20
DV16 <= 24.DB_MAX_OUTPUT_PORT_TYPE
CLR => 20.IN0
G => 29.IN0
G => 21~0.IN0
CLK => 21.CLK
CLK => 22.CLK
CLK => 23.CLK
CLK => 24.CLK
DV8 <= 23.DB_MAX_OUTPUT_PORT_TYPE
DV4 <= 22.DB_MAX_OUTPUT_PORT_TYPE
DV2 <= 21.DB_MAX_OUTPUT_PORT_TYPE


|graber|CLOCK:inst45|freqdiv:inst19
DV16 <= 24.DB_MAX_OUTPUT_PORT_TYPE
CLR => 20.IN0
G => 29.IN0
G => 21~0.IN0
CLK => 21.CLK
CLK => 22.CLK
CLK => 23.CLK
CLK => 24.CLK
DV8 <= 23.DB_MAX_OUTPUT_PORT_TYPE
DV4 <= 22.DB_MAX_OUTPUT_PORT_TYPE
DV2 <= 21.DB_MAX_OUTPUT_PORT_TYPE


|graber|CLOCK:inst45|freqdiv:inst16
DV16 <= 24.DB_MAX_OUTPUT_PORT_TYPE
CLR => 20.IN0
G => 29.IN0
G => 21~0.IN0
CLK => 21.CLK
CLK => 22.CLK
CLK => 23.CLK
CLK => 24.CLK
DV8 <= 23.DB_MAX_OUTPUT_PORT_TYPE
DV4 <= 22.DB_MAX_OUTPUT_PORT_TYPE
DV2 <= 21.DB_MAX_OUTPUT_PORT_TYPE


|graber|CLOCK:inst45|freqdiv:inst6
DV16 <= 24.DB_MAX_OUTPUT_PORT_TYPE
CLR => 20.IN0
G => 29.IN0
G => 21~0.IN0
CLK => 21.CLK
CLK => 22.CLK
CLK => 23.CLK
CLK => 24.CLK
DV8 <= 23.DB_MAX_OUTPUT_PORT_TYPE
DV4 <= 22.DB_MAX_OUTPUT_PORT_TYPE
DV2 <= 21.DB_MAX_OUTPUT_PORT_TYPE


|graber|CLOCK:inst45|freqdiv:inst3
DV16 <= 24.DB_MAX_OUTPUT_PORT_TYPE
CLR => 20.IN0
G => 29.IN0
G => 21~0.IN0
CLK => 21.CLK
CLK => 22.CLK
CLK => 23.CLK
CLK => 24.CLK
DV8 <= 23.DB_MAX_OUTPUT_PORT_TYPE
DV4 <= 22.DB_MAX_OUTPUT_PORT_TYPE
DV2 <= 21.DB_MAX_OUTPUT_PORT_TYPE


|graber|CLOCK:inst45|freqdiv:inst1
DV16 <= 24.DB_MAX_OUTPUT_PORT_TYPE
CLR => 20.IN0
G => 29.IN0
G => 21~0.IN0
CLK => 21.CLK
CLK => 22.CLK
CLK => 23.CLK
CLK => 24.CLK
DV8 <= 23.DB_MAX_OUTPUT_PORT_TYPE
DV4 <= 22.DB_MAX_OUTPUT_PORT_TYPE
DV2 <= 21.DB_MAX_OUTPUT_PORT_TYPE


|graber|bit8_PortIn:inst5
D[0] <= inst44[0]
D[1] <= inst44[1]
D[2] <= inst44[2]
D[3] <= inst44[3]
D[4] <= inst44[4]
D[5] <= inst44[5]
D[6] <= inst44[6]
D[7] <= inst44[7]
CLK_H1 => inst50.IN0
IN[0] => inst43[0].DATAIN
IN[1] => inst43[1].DATAIN
IN[2] => inst43[2].DATAIN
IN[3] => inst43[3].DATAIN
IN[4] => inst43[4].DATAIN
IN[5] => inst43[5].DATAIN
IN[6] => inst43[6].DATAIN
IN[7] => inst43[7].DATAIN
-IORD => inst1.IN0
DSP_nCS => inst1.IN1


|graber|bit8_PortIn:inst4
D[0] <= inst44[0]
D[1] <= inst44[1]
D[2] <= inst44[2]
D[3] <= inst44[3]
D[4] <= inst44[4]
D[5] <= inst44[5]
D[6] <= inst44[6]
D[7] <= inst44[7]
CLK_H1 => inst50.IN0
IN[0] => inst43[0].DATAIN
IN[1] => inst43[1].DATAIN
IN[2] => inst43[2].DATAIN
IN[3] => inst43[3].DATAIN
IN[4] => inst43[4].DATAIN
IN[5] => inst43[5].DATAIN
IN[6] => inst43[6].DATAIN
IN[7] => inst43[7].DATAIN
-IORD => inst1.IN0
DSP_nCS => inst1.IN1


|graber|addr_part:inst8
LLC2 => count19:U1.LLC2
SEC => addr_sec:U2.SEC_ADDR
SEC => count19:U1.SEC
HREF => count19:U1.HREF_I
VREF => count19:U1.RESET
DSP_ADDR[0] => addr_sec:U2.DSP_ADDR_I[0]
DSP_ADDR[1] => addr_sec:U2.DSP_ADDR_I[1]
DSP_ADDR[2] => addr_sec:U2.DSP_ADDR_I[2]
DSP_ADDR[3] => addr_sec:U2.DSP_ADDR_I[3]
DSP_ADDR[4] => addr_sec:U2.DSP_ADDR_I[4]
DSP_ADDR[5] => addr_sec:U2.DSP_ADDR_I[5]
DSP_ADDR[6] => addr_sec:U2.DSP_ADDR_I[6]
DSP_ADDR[7] => addr_sec:U2.DSP_ADDR_I[7]
DSP_ADDR[8] => addr_sec:U2.DSP_ADDR_I[8]
DSP_ADDR[9] => addr_sec:U2.DSP_ADDR_I[9]
DSP_ADDR[10] => addr_sec:U2.DSP_ADDR_I[10]
DSP_ADDR[11] => addr_sec:U2.DSP_ADDR_I[11]
DSP_ADDR[12] => addr_sec:U2.DSP_ADDR_I[12]
DSP_ADDR[13] => addr_sec:U2.DSP_ADDR_I[13]
DSP_ADDR[14] => addr_sec:U2.DSP_ADDR_I[14]
DSP_ADDR[15] => addr_sec:U2.DSP_ADDR_I[15]
DSP_ADDR[16] => addr_sec:U2.DSP_ADDR_I[16]
DSP_ADDR[17] => addr_sec:U2.DSP_ADDR_I[17]
DSP_ADDR[18] => addr_sec:U2.DSP_ADDR_I[18]
RAM_ADDR[0] <= addr_sec:U2.RAM_ADDR_I[0]
RAM_ADDR[1] <= addr_sec:U2.RAM_ADDR_I[1]
RAM_ADDR[2] <= addr_sec:U2.RAM_ADDR_I[2]
RAM_ADDR[3] <= addr_sec:U2.RAM_ADDR_I[3]
RAM_ADDR[4] <= addr_sec:U2.RAM_ADDR_I[4]
RAM_ADDR[5] <= addr_sec:U2.RAM_ADDR_I[5]
RAM_ADDR[6] <= addr_sec:U2.RAM_ADDR_I[6]
RAM_ADDR[7] <= addr_sec:U2.RAM_ADDR_I[7]
RAM_ADDR[8] <= addr_sec:U2.RAM_ADDR_I[8]
RAM_ADDR[9] <= addr_sec:U2.RAM_ADDR_I[9]
RAM_ADDR[10] <= addr_sec:U2.RAM_ADDR_I[10]
RAM_ADDR[11] <= addr_sec:U2.RAM_ADDR_I[11]
RAM_ADDR[12] <= addr_sec:U2.RAM_ADDR_I[12]
RAM_ADDR[13] <= addr_sec:U2.RAM_ADDR_I[13]
RAM_ADDR[14] <= addr_sec:U2.RAM_ADDR_I[14]
RAM_ADDR[15] <= addr_sec:U2.RAM_ADDR_I[15]
RAM_ADDR[16] <= addr_sec:U2.RAM_ADDR_I[16]
RAM_ADDR[17] <= addr_sec:U2.RAM_ADDR_I[17]
RAM_ADDR[18] <= addr_sec:U2.RAM_ADDR_I[18]


|graber|addr_part:inst8|count19:U1
SEC => ~NO_FANOUT~
LLC2 => ADDRESS[0]~reg0.CLK
LLC2 => ADDRESS[1]~reg0.CLK
LLC2 => ADDRESS[2]~reg0.CLK
LLC2 => ADDRESS[3]~reg0.CLK
LLC2 => ADDRESS[4]~reg0.CLK
LLC2 => ADDRESS[5]~reg0.CLK
LLC2 => ADDRESS[6]~reg0.CLK
LLC2 => ADDRESS[7]~reg0.CLK
LLC2 => ADDRESS[8]~reg0.CLK
LLC2 => ADDRESS[9]~reg0.CLK
LLC2 => ADDRESS[10]~reg0.CLK
LLC2 => ADDRESS[11]~reg0.CLK
LLC2 => ADDRESS[12]~reg0.CLK
LLC2 => ADDRESS[13]~reg0.CLK
LLC2 => ADDRESS[14]~reg0.CLK
LLC2 => ADDRESS[15]~reg0.CLK
LLC2 => ADDRESS[16]~reg0.CLK
LLC2 => ADDRESS[17]~reg0.CLK
LLC2 => ADDRESS[18]~reg0.CLK
HREF_I => ADDRESS[0]~reg0.ENA
HREF_I => ADDRESS[1]~reg0.ENA
HREF_I => ADDRESS[2]~reg0.ENA
HREF_I => ADDRESS[3]~reg0.ENA
HREF_I => ADDRESS[4]~reg0.ENA
HREF_I => ADDRESS[5]~reg0.ENA
HREF_I => ADDRESS[6]~reg0.ENA
HREF_I => ADDRESS[7]~reg0.ENA
HREF_I => ADDRESS[8]~reg0.ENA
HREF_I => ADDRESS[9]~reg0.ENA
HREF_I => ADDRESS[10]~reg0.ENA
HREF_I => ADDRESS[11]~reg0.ENA
HREF_I => ADDRESS[12]~reg0.ENA
HREF_I => ADDRESS[13]~reg0.ENA
HREF_I => ADDRESS[14]~reg0.ENA
HREF_I => ADDRESS[15]~reg0.ENA
HREF_I => ADDRESS[16]~reg0.ENA
HREF_I => ADDRESS[17]~reg0.ENA
HREF_I => ADDRESS[18]~reg0.ENA
RESET => ADDRESS[0]~reg0.ACLR
RESET => ADDRESS[1]~reg0.ACLR
RESET => ADDRESS[2]~reg0.ACLR
RESET => ADDRESS[3]~reg0.ACLR
RESET => ADDRESS[4]~reg0.ACLR
RESET => ADDRESS[5]~reg0.ACLR
RESET => ADDRESS[6]~reg0.ACLR
RESET => ADDRESS[7]~reg0.ACLR
RESET => ADDRESS[8]~reg0.ACLR
RESET => ADDRESS[9]~reg0.ACLR
RESET => ADDRESS[10]~reg0.ACLR
RESET => ADDRESS[11]~reg0.ACLR
RESET => ADDRESS[12]~reg0.ACLR
RESET => ADDRESS[13]~reg0.ACLR
RESET => ADDRESS[14]~reg0.ACLR
RESET => ADDRESS[15]~reg0.ACLR
RESET => ADDRESS[16]~reg0.ACLR
RESET => ADDRESS[17]~reg0.ACLR
RESET => ADDRESS[18]~reg0.ACLR
ADDRESS[0] <= ADDRESS[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[1] <= ADDRESS[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[2] <= ADDRESS[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[3] <= ADDRESS[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[4] <= ADDRESS[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[5] <= ADDRESS[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[6] <= ADDRESS[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[7] <= ADDRESS[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[8] <= ADDRESS[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[9] <= ADDRESS[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[10] <= ADDRESS[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[11] <= ADDRESS[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[12] <= ADDRESS[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[13] <= ADDRESS[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[14] <= ADDRESS[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[15] <= ADDRESS[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[16] <= ADDRESS[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[17] <= ADDRESS[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDRESS[18] <= ADDRESS[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|graber|addr_part:inst8|addr_sec:U2
SEC_ADDR => RAM_ADDR_I~0.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~1.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~2.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~3.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~4.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~5.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~6.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~7.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~8.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~9.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~10.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~11.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~12.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~13.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~14.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~15.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~16.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~17.OUTPUTSELECT
SEC_ADDR => RAM_ADDR_I~18.OUTPUTSELECT
GRAB_ADDR_I[0] => RAM_ADDR_I~18.DATAB
GRAB_ADDR_I[1] => RAM_ADDR_I~17.DATAB
GRAB_ADDR_I[2] => RAM_ADDR_I~16.DATAB
GRAB_ADDR_I[3] => RAM_ADDR_I~15.DATAB
GRAB_ADDR_I[4] => RAM_ADDR_I~14.DATAB
GRAB_ADDR_I[5] => RAM_ADDR_I~13.DATAB
GRAB_ADDR_I[6] => RAM_ADDR_I~12.DATAB
GRAB_ADDR_I[7] => RAM_ADDR_I~11.DATAB
GRAB_ADDR_I[8] => RAM_ADDR_I~10.DATAB
GRAB_ADDR_I[9] => RAM_ADDR_I~9.DATAB
GRAB_ADDR_I[10] => RAM_ADDR_I~8.DATAB
GRAB_ADDR_I[11] => RAM_ADDR_I~7.DATAB
GRAB_ADDR_I[12] => RAM_ADDR_I~6.DATAB
GRAB_ADDR_I[13] => RAM_ADDR_I~5.DATAB
GRAB_ADDR_I[14] => RAM_ADDR_I~4.DATAB
GRAB_ADDR_I[15] => RAM_ADDR_I~3.DATAB
GRAB_ADDR_I[16] => RAM_ADDR_I~2.DATAB
GRAB_ADDR_I[17] => RAM_ADDR_I~1.DATAB
GRAB_ADDR_I[18] => RAM_ADDR_I~0.DATAB
DSP_ADDR_I[0] => RAM_ADDR_I~18.DATAA
DSP_ADDR_I[1] => RAM_ADDR_I~17.DATAA
DSP_ADDR_I[2] => RAM_ADDR_I~16.DATAA
DSP_ADDR_I[3] => RAM_ADDR_I~15.DATAA
DSP_ADDR_I[4] => RAM_ADDR_I~14.DATAA
DSP_ADDR_I[5] => RAM_ADDR_I~13.DATAA
DSP_ADDR_I[6] => RAM_ADDR_I~12.DATAA
DSP_ADDR_I[7] => RAM_ADDR_I~11.DATAA
DSP_ADDR_I[8] => RAM_ADDR_I~10.DATAA
DSP_ADDR_I[9] => RAM_ADDR_I~9.DATAA
DSP_ADDR_I[10] => RAM_ADDR_I~8.DATAA
DSP_ADDR_I[11] => RAM_ADDR_I~7.DATAA
DSP_ADDR_I[12] => RAM_ADDR_I~6.DATAA
DSP_ADDR_I[13] => RAM_ADDR_I~5.DATAA
DSP_ADDR_I[14] => RAM_ADDR_I~4.DATAA
DSP_ADDR_I[15] => RAM_ADDR_I~3.DATAA
DSP_ADDR_I[16] => RAM_ADDR_I~2.DATAA
DSP_ADDR_I[17] => RAM_ADDR_I~1.DATAA
DSP_ADDR_I[18] => RAM_ADDR_I~0.DATAA
RAM_ADDR_I[0] <= RAM_ADDR_I~18.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[1] <= RAM_ADDR_I~17.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[2] <= RAM_ADDR_I~16.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[3] <= RAM_ADDR_I~15.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[4] <= RAM_ADDR_I~14.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[5] <= RAM_ADDR_I~13.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[6] <= RAM_ADDR_I~12.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[7] <= RAM_ADDR_I~11.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[8] <= RAM_ADDR_I~10.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[9] <= RAM_ADDR_I~9.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[10] <= RAM_ADDR_I~8.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[11] <= RAM_ADDR_I~7.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[12] <= RAM_ADDR_I~6.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[13] <= RAM_ADDR_I~5.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[14] <= RAM_ADDR_I~4.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[15] <= RAM_ADDR_I~3.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[16] <= RAM_ADDR_I~2.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[17] <= RAM_ADDR_I~1.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR_I[18] <= RAM_ADDR_I~0.DB_MAX_OUTPUT_PORT_TYPE