graber.map.qmsg

Source of Grabber Board

{ "Warning" "WSGN_SEARCH_FILE" "addr_part.vhd 2 1 " "Warning: Using design file addr_part.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 addr_part-honey " "Info: Found design unit 1: addr_part-honey" {  } { { "addr_part.vhd" "" { Text "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/addr_part.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 addr_part " "Info: Found entity 1: addr_part" {  } { { "addr_part.vhd" "" { Text "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/addr_part.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addr_part addr_part:inst8 " "Info: Elaborating entity \"addr_part\" for hierarchy \"addr_part:inst8\"" {  } { { "graber.bdf" "inst8" { Schematic "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/graber.bdf" { { 368 1792 2032 496 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "count19.vhd 2 1 " "Warning: Using design file count19.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count19-honey " "Info: Found design unit 1: count19-honey" {  } { { "count19.vhd" "" { Text "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/count19.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 count19 " "Info: Found entity 1: count19" {  } { { "count19.vhd" "" { Text "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/count19.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count19 addr_part:inst8\|count19:U1 " "Info: Elaborating entity \"count19\" for hierarchy \"addr_part:inst8\|count19:U1\"" {  } { { "addr_part.vhd" "U1" { Text "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/addr_part.vhd" 27 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "addr_sec.vhd 2 1 " "Warning: Using design file addr_sec.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 addr_sec-honey " "Info: Found design unit 1: addr_sec-honey" {  } { { "addr_sec.vhd" "" { Text "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/addr_sec.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 addr_sec " "Info: Found entity 1: addr_sec" {  } { { "addr_sec.vhd" "" { Text "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/addr_sec.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addr_sec addr_part:inst8\|addr_sec:U2 " "Info: Elaborating entity \"addr_sec\" for hierarchy \"addr_part:inst8\|addr_sec:U2\"" {  } { { "addr_part.vhd" "U2" { Text "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/addr_part.vhd" 28 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "addr_part:inst8\|count19:U1\|ADDRESS\[0\]~0 19 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=19) from the following logic: \"addr_part:inst8\|count19:U1\|ADDRESS\[0\]~0\"" {  } { { "count19.vhd" "ADDRESS\[0\]~0" { Text "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/count19.vhd" 17 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "addr_part:inst8\|count19:U1\|lpm_counter:ADDRESS_rtl_0 " "Info: Elaborated megafunction instantiation \"addr_part:inst8\|count19:U1\|lpm_counter:ADDRESS_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../../../../altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../../../../altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "addr_part:inst8\|count19:U1\|lpm_counter:ADDRESS_rtl_0\|alt_counter_f10ke:wysi_counter addr_part:inst8\|count19:U1\|lpm_counter:ADDRESS_rtl_0 " "Info: Elaborated megafunction instantiation \"addr_part:inst8\|count19:U1\|lpm_counter:ADDRESS_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"addr_part:inst8\|count19:U1\|lpm_counter:ADDRESS_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 410 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "addr_part:inst8\|count19:U1\|lpm_counter:ADDRESS_rtl_0 " "Info: Instantiated megafunction \"addr_part:inst8\|count19:U1\|lpm_counter:ADDRESS_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 19 " "Info: Parameter \"LPM_WIDTH\" = \"19\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "WE_ " "Warning: No output dependent on input pin \"WE_\"" {  } { { "graber.bdf" "" { Schematic "C:/Documents and Settings/Administrator/官帕 拳搁/凉累包访/厚陵倔 飘饭侨/橇肺弊伐/家胶/VHDL/graber.bdf" { { -56 80 248 -40 "WE_" "" } { -64 248 336 -48 "WE_" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "183 " "Info: Implemented 183 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "44 " "Info: Implemented 44 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "40 " "Info: Implemented 40 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "99 " "Info: Implemented 99 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 25 19:02:07 2009 " "Info: Processing ended: Wed Feb 25 19:02:07 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}