bit8_portin.tan.qmsg

Source of Grabber Board

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK_H1 D\[1\] inst43\[1\] 10.900 ns register " "Info: tco from clock CLK_H1 to destination pin D\[1\] through register inst43\[1\] is 10.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_H1 source 3.900 ns + Longest register " "Info: + Longest clock path from clock CLK_H1 to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK_H1 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK_H1'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "" { CLK_H1 } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 56 56 224 72 "CLK_H1" "" } { 328 96 168 344 "CLK_H1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns inst43\[1\] 2 REG LC8_A16 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_A16; Fanout = 1; REG Node = 'inst43\[1\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "2.000 ns" { CLK_H1 inst43[1] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.900 ns" { CLK_H1 inst43[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest register pin " "Info: + Longest register to pin delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst43\[1\] 1 REG LC8_A16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A16; Fanout = 1; REG Node = 'inst43\[1\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "" { inst43[1] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(3.900 ns) 6.100 ns D\[1\] 2 PIN PIN_70 0 " "Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'D\[1\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "6.100 ns" { inst43[1] D[1] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 96 440 616 112 "D\[7..0\]" "" } { 296 600 680 312 "D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 63.93 % " "Info: Total cell delay = 3.900 ns ( 63.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 36.07 % " "Info: Total interconnect delay = 2.200 ns ( 36.07 % )" {  } {  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "6.100 ns" { inst43[1] D[1] } "NODE_NAME" } } }  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.900 ns" { CLK_H1 inst43[1] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "6.100 ns" { inst43[1] D[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "-IORD D\[4\] 14.800 ns Longest " "Info: Longest tpd from source pin -IORD to destination pin D\[4\] is 14.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns -IORD 1 PIN PIN_84 1 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_84; Fanout = 1; PIN Node = '-IORD'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "" { -IORD } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 104 56 224 120 "-IORD" "" } { 232 264 360 248 "-IORD" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.900 ns) 5.400 ns inst1 2 COMB LC1_C11 8 " "Info: 2: + IC(1.600 ns) + CELL(1.900 ns) = 5.400 ns; Loc. = LC1_C11; Fanout = 8; COMB Node = 'inst1'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.500 ns" { -IORD inst1 } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 216 360 424 264 "inst1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(5.000 ns) 14.800 ns D\[4\] 3 PIN PIN_59 0 " "Info: 3: + IC(4.400 ns) + CELL(5.000 ns) = 14.800 ns; Loc. = PIN_59; Fanout = 0; PIN Node = 'D\[4\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "9.400 ns" { inst1 D[4] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 96 440 616 112 "D\[7..0\]" "" } { 296 600 680 312 "D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.800 ns 59.46 % " "Info: Total cell delay = 8.800 ns ( 59.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 40.54 % " "Info: Total interconnect delay = 6.000 ns ( 40.54 % )" {  } {  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "14.800 ns" { -IORD inst1 D[4] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "inst43\[6\] IN\[6\] CLK_H1 1.000 ns register " "Info: th for register inst43\[6\] (data pin = IN\[6\], clock pin = CLK_H1) is 1.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_H1 destination 3.900 ns + Longest register " "Info: + Longest clock path from clock CLK_H1 to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK_H1 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK_H1'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "" { CLK_H1 } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 56 56 224 72 "CLK_H1" "" } { 328 96 168 344 "CLK_H1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns inst43\[6\] 2 REG LC1_B24 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B24; Fanout = 1; REG Node = 'inst43\[6\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "2.000 ns" { CLK_H1 inst43[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.900 ns" { CLK_H1 inst43[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns IN\[6\] 1 PIN PIN_42 1 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'IN\[6\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "" { IN[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 160 56 224 176 "IN\[7..0\]" "" } { 296 96 168 312 "IN\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.900 ns) 4.300 ns inst43\[6\] 2 REG LC1_B24 1 " "Info: 2: + IC(1.500 ns) + CELL(0.900 ns) = 4.300 ns; Loc. = LC1_B24; Fanout = 1; REG Node = 'inst43\[6\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "2.400 ns" { IN[6] inst43[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 65.12 % " "Info: Total cell delay = 2.800 ns ( 65.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 34.88 % " "Info: Total interconnect delay = 1.500 ns ( 34.88 % )" {  } {  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "4.300 ns" { IN[6] inst43[6] } "NODE_NAME" } } }  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.900 ns" { CLK_H1 inst43[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "4.300 ns" { IN[6] inst43[6] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK_H1 D\[6\] inst43\[6\] 9.900 ns register " "Info: Minimum tco from clock CLK_H1 to destination pin D\[6\] through register inst43\[6\] is 9.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_H1 source 3.900 ns + Shortest register " "Info: + Shortest clock path from clock CLK_H1 to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK_H1 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK_H1'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "" { CLK_H1 } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 56 56 224 72 "CLK_H1" "" } { 328 96 168 344 "CLK_H1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns inst43\[6\] 2 REG LC1_B24 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B24; Fanout = 1; REG Node = 'inst43\[6\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "2.000 ns" { CLK_H1 inst43[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.900 ns" { CLK_H1 inst43[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.100 ns + Shortest register pin " "Info: + Shortest register to pin delay is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst43\[6\] 1 REG LC1_B24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B24; Fanout = 1; REG Node = 'inst43\[6\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "" { inst43[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.900 ns) 5.100 ns D\[6\] 2 PIN PIN_67 0 " "Info: 2: + IC(1.200 ns) + CELL(3.900 ns) = 5.100 ns; Loc. = PIN_67; Fanout = 0; PIN Node = 'D\[6\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "5.100 ns" { inst43[6] D[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 96 440 616 112 "D\[7..0\]" "" } { 296 600 680 312 "D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 76.47 % " "Info: Total cell delay = 3.900 ns ( 76.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 23.53 % " "Info: Total interconnect delay = 1.200 ns ( 23.53 % )" {  } {  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "5.100 ns" { inst43[6] D[6] } "NODE_NAME" } } }  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.900 ns" { CLK_H1 inst43[6] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "5.100 ns" { inst43[6] D[6] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "DSP_nCS D\[2\] 14.000 ns Shortest " "Info: Shortest tpd from source pin DSP_nCS to destination pin D\[2\] is 14.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns DSP_nCS 1 PIN PIN_2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_2; Fanout = 1; PIN Node = 'DSP_nCS'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "" { DSP_nCS } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 80 56 224 96 "DSP_nCS" "" } { 216 264 360 232 "DSP_nCS" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.400 ns) 4.900 ns inst1 2 COMB LC1_C11 8 " "Info: 2: + IC(1.600 ns) + CELL(1.400 ns) = 4.900 ns; Loc. = LC1_C11; Fanout = 8; COMB Node = 'inst1'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.000 ns" { DSP_nCS inst1 } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 216 360 424 264 "inst1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(5.000 ns) 14.000 ns D\[2\] 3 PIN PIN_71 0 " "Info: 3: + IC(4.100 ns) + CELL(5.000 ns) = 14.000 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'D\[2\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "9.100 ns" { inst1 D[2] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 96 440 616 112 "D\[7..0\]" "" } { 296 600 680 312 "D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.300 ns 59.29 % " "Info: Total cell delay = 8.300 ns ( 59.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.700 ns 40.71 % " "Info: Total interconnect delay = 5.700 ns ( 40.71 % )" {  } {  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "14.000 ns" { DSP_nCS inst1 D[2] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 09 01:06:36 2006 " "Info: Processing ended: Sat Sep 09 01:06:36 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}